Table Of Contents - Fujitsu MB91F109 FR30 Hardware Manual

CONTENTS
CHAPTER 1 OVERVIEW ................................................................................................... 1
1.1 MB91F109 Characteristics .................................................................................................................... 2
1.2 General Block Diagram of MB91F109 ................................................................................................... 6
1.3 Outside Dimensions ............................................................................................................................... 7
1.4 Pin Arrangement Diagrams ................................................................................................................. 10
1.5 Pin Functions ....................................................................................................................................... 14
1.6 I/O Circuit Format ................................................................................................................................ 22
1.7 Memory Address Space ...................................................................................................................... 24
1.8 Handling of Devices ............................................................................................................................. 26
CHAPTER 2 CPU ............................................................................................................. 29
2.1 CPU Architecture ................................................................................................................................. 30
2.2 Internal Architecture ............................................................................................................................. 31
2.3 Programming Model ............................................................................................................................ 33
2.3.1 General-Purpose Registers ............................................................................................................ 35
2.3.2 Special Registers ............................................................................................................................ 36
2.3.3 Program Status Register (PS) ........................................................................................................ 39
2.4 Data Structure ...................................................................................................................................... 42
2.5 Word Alignment ................................................................................................................................... 43
2.6 Memory Map ........................................................................................................................................ 44
2.7 Instruction Overview ............................................................................................................................ 46
2.7.1 Branch Instructions with Delay Slots .............................................................................................. 48
2.7.2 Branch Instructions without Delay Slots ......................................................................................... 51
2.8 EIT (Exception, Interrupt, and Trap) .................................................................................................... 52
2.8.1 EIT Interrupt Levels ........................................................................................................................ 54
2.8.2 Interrupt Control Register (ICR) ...................................................................................................... 56
2.8.3 System Stack Pointer (SSP) ........................................................................................................... 57
2.8.4 Interrupt Stack ................................................................................................................................ 58
2.8.5 Table Base Register (TBR) ............................................................................................................ 59
2.8.6 EIT Vector Table ............................................................................................................................. 60
2.8.7 Multiple EIT Processing .................................................................................................................. 62
2.8.8 EIT Operation ................................................................................................................................. 64
2.9 Reset Sequence .................................................................................................................................. 68
2.10 Operation Mode ................................................................................................................................... 69
CHAPTER 3 CLOCK GENERATOR AND CONTROLLER ............................................. 73
3.1 Outline of Clock Generator and Controller ........................................................................................... 74
3.2 Reset Reason Resister (RSRR) and Watchdog Cycle Control Register (WTCR) ............................... 76
3.3 Standby Control Register (STCR) ....................................................................................................... 78
3.4 DMA Request Suppression Register (PDRR) ..................................................................................... 80
3.5 Timebase Timer Clear Register (CTBR) .............................................................................................. 81
3.6 Gear Control Register (GCR) .............................................................................................................. 82
3.7 Watchdog Timer Reset Delay Register (WPR) .................................................................................... 85
3.8 PLL Control Register (PCTR) .............................................................................................................. 86
vii