Counter States; Figure 12.5-1 Counter States Transition - Fujitsu MB91F109 FR30 Hardware Manual

12.5 Counter States

The states of the counter are determined by the CNTE bit of the control register and
the internal Wait signal as follows:
CNTE = "0", Wait = "1": Stop state
CNTE = "1", Wait = "1": Wait state (start trigger wait state)
CNTE = "1", Wait = "0": Run state
Figure 12.5-1 is a state transition diagram.
Counter States
RESET
' CNTE='0'
C NTE=1 ,WAIT =1
WAIT
Counter: Holds the value at a stop.
The value is undefined immediately
after resetting until loading.

Figure 12.5-1 Counter States Transition

C N TE =0 , W AIT = 1
STO P
Counter: Holds the value at a stop.
Immediately after resetting, this value
is undefined.
CNTE='1 '
TRG='0'
RE L D U F
TRG='1 '
LO AD C N TE =1 , W AIT = 0
The contents of the reload register
are loaded to the counter.
State transition by hardware
State transition by register access
C N T E= '0 '
C N T E ='1 '
T R G= '1 '
C N T E =1 , WA IT = 0
R U N
Counter: Operates
T R G= '1 '
R E L D U F
12.5 Counter States
Loading is completed.
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