Table of Contents
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CHAPTER 4
This chapter explains the basic items of the external bus interface, register
configuration and functions, bus operations, and bus timing and provides bus
operation program samples.
4.1 Outline of Bus Interface
4.2 Chip Select Area
4.3 Bus Interface
4.4 Area Select Register (ASR) and Area Mask Register (AMR)
4.5 Area Mode Register 0 (AMD0)
4.6 Area Mode Register 1 (AMD1)
4.7 Area Mode Register 32 (AMD32)
4.8 Area Mode Register 4 (AMD4)
4.9 Area Mode Register 5 (AMD5)
4.10 DRAM Control Register 4/5 (DMCR4/5)
4.11 Refresh Control Register (RFCR)
4.12 External Pin Control Register 0 (EPCR0)
4.13 External Pin Control Register 1 (EPCR1)
4.14 DRAM Signal Control Register (DSCR)
4.15 Little Endian Register (LER)
4.16 Relationship between Data Bus Widths and Control Signals
4.17 Bus Timing
4.18 Internal Clock Multiplication (Clock Doubler)
4.19 Program Example for External Bus Operation
BUS INTERFACE
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