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Intel XScale® Core Developer's Manual
Configuration
7.3.2
Clock and Power Management Registers
These registers contain functions for managing the core clock and power.
Power management modes are supported through the PWRMODE Register (CRn = 0x7, CRm =
0x0). The function and definition of these modes is defined by the ASSP. The user should refer to
the Intel XScale
specifics on the use of these registers.
To enter any of these modes, write the appropriate data to the PWRMODE register. Software may
read this register, but since software only runs during ACTIVE mode, it will always read zeroes
from the M field.
Table 7-23.
PWRMODE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: writable bits set to 0
Bits
31:4
3:0
Software can change core clock frequency by writing to the CCLKCFG register (CRn = 0x6, CRm
= 0x0). This function informs the clocking unit (located external to the core) to change core clock
frequency. Software can read CCLKCFG to determine current operating frequency. Exact
definition of this register can be found in the Intel XScale
the ASSP architecture specification.
Table 7-24.
Clock and Power Management
Power Mode Function
(Defined by ASSP)
Read CCLKCFG
Write CCLKCFG
Table 7-25.
CCLKCFG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: unpredictable
Bits
31:4
3:0
98
®
core implementation option section of the ASSP architecture specification for
Access
Read-unpredictable / Write-as-Zero
Read / Write
Function
Access
Read-unpredictable / Write-as-Zero
Read / Write
January, 2004
Reserved
Mode (M)
0 = ACTIVE
All other values are defined by the ASSP
®
core implementation option section of
Data
Defined by ASSP
ignored
CCLKCFG value
Reserved
Core Clock Configuration (CCLKCFG)
This field is used to configure the core clock frequency
and is defined by the ASSP.
8
7
6
5
4
3
2
M
Description
Instruction
MCR p14, 0, Rd, c7, c0, 0
MRC p14, 0, Rd, c6, c0, 0
MCR p14, 0, Rd, c6, c0, 0
8
7
6
5
4
3
2
CCLKCFG
Description
Developer's Manual
1
0
1
0
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