Register 8: Tlb Operations; Tlb Functions - Intel XScale Core Developer's Manual

7.2.9

Register 8: TLB Operations

Disabling/enabling the MMU has no effect on the contents of either TLB: valid entries stay valid,
locked items remain locked. All operations defined in
TLB is enabled or disabled.
This register should be accessed as write-only. Reads from this register, as with an MRC, have an
undefined effect.
Table 7-13.

TLB Functions

Invalidate I&D TLB
Invalidate I TLB
Invalidate I TLB entry
Invalidate D TLB
Invalidate D TLB entry
Developer's Manual
Function opcode_2
0b000
0b000
0b001
0b000
0b001
January, 2004
Intel XScale® Core Developer's Manual
Table 7-13 work regardless of whether the
CRm Data
0b0111 Ignored
0b0101 Ignored
0b0101 MVA
0b0110 Ignored
0b0110 MVA
Configuration
Instruction
MCR p15, 0, Rd, c8, c7, 0
MCR p15, 0, Rd, c8, c5, 0
MCR p15, 0, Rd, c8, c5, 1
MCR p15, 0, Rd, c8, c6, 0
MCR p15, 0, Rd, c8, c6, 1
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