Event Architecture; Exception Summary; Event Priority - Intel XScale Core Developer's Manual

Intel XScale® Core Developer's Manual
Programming Model
2.3.4

Event Architecture

2.3.4.1

Exception Summary

Table 2-11
Subsequent sections give details on each exception.
Table 2-11.

Exception Summary

Exception Description
External Instruction
Instruction MMU
Instruction Cache Parity
Lock Abort
MMU Data
External Data
Data Cache Parity
Software Interrupt
Undefined Instruction
Debug Events
a. Exception types are those described in the ARM, section 2.5.
b. Refer to
2.3.4.2

Event Priority

The Intel XScale
Manual. The processor has additional exceptions that might be generated while debugging. For
information on these debug exceptions, see
Table 2-12.

Event Priority

32
shows all the exceptions that the core may generate, and the attributes of each.
Exception Type
Reset Reset
FIQ
IRQ
Prefetch
Prefetch
Prefetch
Data
Data
Data
Data
Software Interrupt
Undefined Instruction
b
varies
Chapter 9, "Software Debug" for more details
®
core follows the exception priority specified in the ARM Architecture Reference
Exception
Reset
Data Abort (Precise & Imprecise)
FIQ
IRQ
Prefetch Abort
Undefined Instruction, SWI
January, 2004
a
Precise?
FIQ
IRQ
varies
Chapter 9, "Software
Updates FAR?
N N
N N
N N
Y N
Y N
Y N
Y N
Y Y
N N
N N
Y N
Y N
N
Debug".
Priority
1 (Highest)
2
3
4
5
6 (Lowest)
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