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Intel XScale® Core Developer's Manual
Performance Monitoring
8.3.3
Performance Monitor Control Register (PMNC)
The performance monitor control register (PMNC) is a coprocessor register that:
•
contains the PMU ID
•
extends CCNT counting by six more bits (cycles between counter rollover = 2
•
resets all counters to zero
•
and enables the entire mechanism
Table 8-8
Table 8-8.
Performance Monitor Control Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: E = 0, ID = 0x14, others unpredictable
Bits
31:24
23:4
3
2
1
0
108
shows the format of the PMNC register.
ID
Access
Read / Write Ignored
Read-unpredictable / Write-as-0
Read / Write
Read-unpredictable / Write
Read-unpredictable / Write
Read / Write
January, 2004
8
Description
Performance Monitor Identification (ID) -
XSC2 = 0x14
Reserved
Clock Counter Divider (D) -
0 = CCNT counts every processor clock cycle
th
1 = CCNT counts every 64
Clock Counter Reset (C) -
0 = no action
1 = reset the clock counter to '0x0'
Performance Counter Reset (P) -
0 = no action
1 = reset all performance counters to '0x0'
Enable (E) -
0 = all counters are disabled
1 = all counters are enabled
38
)
7
6
5
4
3
2
1
0
D C P E
processor clock cycle
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