Checkpoint Registers - Intel XScale Core Developer's Manual

Intel XScale® Core Developer's Manual
Software Debug
9.12.1.1

Checkpoint Registers

When the debugger reconstructs a trace history, it is required to start at the oldest trace buffer entry
and construct a trace going forward. In fill-once mode and wrap-around mode when the buffer does
not wrap around, the trace can be reconstructed by starting from the point in the code where the
trace buffer was first enabled.
The difficulty occurs in wrap-around mode when the trace buffer wraps around at least once. In this
case the debugger gets a snapshot of the last N control flow changes in the program, where N <=
size of buffer. The debugger does not know the starting address of the oldest entry read from the
trace buffer. The checkpoint registers provide reference addresses to help reduce this problem.
Table 9-16. Checkpoint Register (CHKPTx)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: Unpredictable
Bits
31:0
The two checkpoint registers (CHKPT0, CHKPT1) on Elkhart provide the debugger with two
reference addresses to use for re-constructing the trace history.
When the trace buffer is enabled, reading and writing to either checkpoint register has
unpredictable results. When the trace buffer is disabled, writing to a checkpoint register sets the
register to the value written. Reading the checkpoint registers returns the value of the register.
In normal usage, the checkpoint registers are used to hold target addresses of specific entries in the
trace buffer. Only direct and indirect entries get checkpointed. Exception and roll-over messages
are never checkpointed. When an entry is checkpointed, the processor sets bit 6 of the message
byte to indicate this (refer to
When the trace buffer contains only one checkpointed entry, the corresponding checkpoint register
is CHKPT0. When the trace buffer wraps around, two entries will typically be checkpointed,
usually about half a buffers length apart. In this case, the first (oldest) checkpointed entry read from
the trace buffer corresponds to CHKPT1, the second checkpointed entry corresponds to CHKPT0.
Although the checkpoint registers are provided for wrap-around mode, they are still valid in
fill-once mode.
146
Access
Read/Write
Table 9-18, "Message Byte
January, 2004
CHKPTx
Description
CHKPTx :
target address for corresponding entry in trace buffer
Formats")
8 7 6 5 4 3 2 1 0
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