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Intel XScale® Core Developer's Manual
Software Debug
9.14
Downloading Code in the Instruction Cache
On Elkhart, a mini instruction cache, physically separate
used as an on-chip instruction RAM. A debugger can download code directly into either instruction
cache through JTAG. In addition to downloading code, several cache functions are supported.
Elkhart supports loading the instruction cache during reset and dynamically (without resetting the
core). Loading the instruction cache during normal program execution requires a strict
handshaking protocol between software running on Elkhart and the debugger.
In the remainder of this section the term 'instruction cache' applies to either main or mini
instruction cache.
9.14.1
Mini Instruction Cache Overview
The mini instruction cache is a smaller version of the main instruction cache. The size of the mini
instruction cache is proportional to that of the main instruction cache:
A version of the core with a 32KB main instruction cache will have a 2KB mini instruction cache.
A version of the core with a 16KB main instruction cache will have a 1KB mini instruction cache.
Refer to the Intel XScale
Product (ASSP) architecture specification for more details the cache size supported by the ASSP.
The mini instruction cache is a 2-way set associative cache. The 2KB version has 32 sets, the 1KB
version has 16 sets. The line size is 8 words. The cache uses the round-robin replacement policy.
The mini instruction cache is virtually addressed and addresses may be remapped by the PID.
However, since the debug handler executes in Special Debug State, address translation and PID
remapping are turned off. For application code, accesses to the mini instruction cache use the
normal address translation and PID mechanisms.
Normal application code is never cached in the mini instruction cache on an instruction fetch. The
only way to get code into the mini instruction cache is through the JTAG LDIC function. Code
downloaded into the mini instruction cache is essentially locked - it cannot be overwritten by
application code running on Elkhart. However, it is not locked against code downloaded through
the JTAG LDIC functions.
Application code can invalidate a line in the mini instruction cache using a CP15 Invalidate IC line
function to an address that hits in the mini instruction cache. However, a CP15 global invalidate IC
function does not affect the mini instruction cache.
The mini instruction cache can be globally invalidated through JTAG by the LDIC Invalidate IC
function or by a processor reset when the processor is not in HALT or LDIC mode. A single line in
the mini instruction cache can be invalidated through JTAG by the LDIC Invalidate IC-line
function.
1.
A cache line fill from external memory will never be written into the mini-instruction cache. The only way to load a code into the
mini-instruction cache is through JTAG.
154
®
core implementation option section of the Application Specific Standard
January, 2004
1
from the main instruction cache can be
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