The Intel Xscale ® Core Pipeline Organization; A-1 Pipelines And Pipe Stages - Intel XScale Core Developer's Manual

A.2.1.2. The Intel XScale
The Intel XScale
pipeline, and a memory access pipeline. These are shown in
pipeline shaded.
Figure A-1. The Intel XScale
Table A-1
Table A-1. Pipelines and Pipe stages
Pipe / Pipestage
Main Execution Pipeline
IF1/IF2
ID
RF
X1
X2
XWB
Memory Pipeline
D1/D2
DWB
MAC Pipeline
M1-M5
MWB (not shown)
Developer's Manual
®
Core Pipeline Organization
®
core single-issue superpipeline consists of a main execution pipeline, MAC
®
Core RISC Superpipeline
Main execution pipeline
F1 F2 ID
gives a brief description of each pipe-stage.
Handles data processing instructions
Instruction Fetch
Instruction Decode
Register File / Operand Shifter
ALU Execute
State Execute
Write-back
Handles load/store instructions
Data Cache Access
Data cache writeback
Handles all multiply instructions
Multiplier stages
MAC write-back - may occur during M2-M5
January, 2004
Intel XScale® Core Developer's Manual
Figure
Memory pipeline
D1
RF X1 X2
MAC pipeline
M1 M2
Description
Optimization Guide
A-1, with the main execution
D2 DWB
XWB
Mx
Covered In
Section A.2.3
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Section A.2.4
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Section A.2.5
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