Intel XScale Core Developer's Manual page 72

Intel XScale® Core Developer's Manual
Data Cache
Example 6-3. Locking Data into the Data Cache
; R1 contains the virtual address of a region of memory to lock,
; configured with C=1 and B=1
; R0 is the number of 32-byte lines to lock into the data cache. In this
; example 16 lines of data are locked into the cache.
; MMU and data cache are enabled prior to this code.
MACRO DRAIN
MCR P15, 0, R0, C7, C10, 4
ENDM
DRAIN
MOV R2, #0x1
MCR P15,0,R2,C9,C2,0
CPWAIT
MOV R0, #16
LOOP1:
MCR P15,0,R1,C7,C10,1
MCR P15,0,R1, C7,C6,1
LDR R2, [R1], #32
SUBS R0, R0, #1; Decrement loop count
BNE LOOP1
MOV R2, #0x0
MCR P15,0,R2,C9,C2,0
CPWAIT
72
; Put the data cache in lock mode
; Write back the line if it's dirty in the cache
; Flush/Invalidate the line from the cache
; Load and lock 32 bytes of data located at [R1]
; into the data cache. Post-increment the address
; in R1 to the next cache line.
; Turn off data cache locking
; Take the data cache out of lock mode.
January, 2004
; drain pending loads and stores
Developer's Manual