Intel XScale Core Developer's Manual page 5

6.2.4 Round-Robin Replacement Algorithm ................................................................... 68
6.2.5 Parity Protection .................................................................................................... 68
6.2.6 Atomic Accesses ................................................................................................... 68
6.3 Data Cache and Mini-Data Cache Control .........................................................................69
6.3.1 Data Memory State After Reset ............................................................................. 69
6.3.2 Enabling/Disabling .................................................................................................69
6.3.3 Invalidate and Clean Operations ........................................................................... 69
6.3.3.1
6.4 Re-configuring the Data Cache as Data RAM .................................................................... 71
6.5 Write Buffer/Fill Buffer Operation and Control .................................................................... 75
7 Configuration ................................................................................................................................. 77
7.1 Overview ............................................................................................................................. 77
7.2 CP15 Registers................................................................................................................... 80
7.2.1 Register 0: ID & Cache Type Registers ................................................................. 81
7.2.2 Register 1: Control & Auxiliary Control Registers .................................................. 83
7.2.3 Register 2: Translation Table Base Register ......................................................... 85
7.2.4 Register 3: Domain Access Control Register......................................................... 85
7.2.5 Register 4: Reserved ............................................................................................. 85
7.2.6 Register 5: Fault Status Register ........................................................................... 86
7.2.7 Register 6: Fault address Register ........................................................................ 86
7.2.8 Register 7: Cache Functions ................................................................................. 87
7.2.9 Register 8: TLB Operations ................................................................................... 89
7.2.10 Register 9: Cache Lock Down ............................................................................... 90
7.2.11 Register 10: TLB Lock Down ................................................................................. 91
7.2.12 Register 11-12: Reserved ...................................................................................... 91
7.2.13 Register 13: Process ID ......................................................................................... 91
7.2.13.1 The PID Register Affect On Addresses ................................................. 92
7.2.14 Register 14: Breakpoint Registers .........................................................................93
7.2.15 Register 15: Coprocessor Access Register ...........................................................94
7.3 CP14 Registers................................................................................................................... 96
7.3.1 Performance Monitoring Registers ........................................................................ 96
7.3.1.1
7.3.1.2
7.3.2 Clock and Power Management Registers.............................................................. 98
7.3.3 Software Debug Registers .....................................................................................99
8 Performance Monitoring .............................................................................................................. 101
8.1 Overview ........................................................................................................................... 101
8.2 XSC1 Register Description (2 counter variant) ................................................................. 102
8.2.1 Clock Counter (CCNT; CP14 - Register 1) .......................................................... 102
8.2.2 Performance Count Registers (PMN0 - PMN1;
CP14 - Register 2 and 3, Respectively)............................................................... 103
8.2.3 Extending Count Duration Beyond 32 Bits .......................................................... 103
8.2.4 Performance Monitor Control Register (PMNC) ..................................................103
8.2.4.1
8.3 XSC2 Register Description (4 counter variant) ................................................................. 106
8.3.1 Clock Counter (CCNT)......................................................................................... 106
8.3.2 Performance Count Registers (PMN0 - PMN3) ................................................... 107
8.3.3 Performance Monitor Control Register (PMNC) ..................................................108
8.3.4 Interrupt Enable Register (INTEN).......................................................................109
Developer's Manual
Global Clean and Invalidate Operation .................................................. 70
XSC1 Performance Monitoring Registers .............................................. 96
XSC2 Performance Monitoring Registers .............................................. 97
Managing PMNC.................................................................................. 105
January, 2004
Intel XScale® Core Developer's Manual
Contents
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