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Intel XScale® Core Developer's Manual
Software Debug
9.6
HW Breakpoint Resources
The Elkhart debug architecture defines two instruction and two data breakpoint registers, denoted
IBCR0, IBCR1, DBR0, and DBR1.
The instruction and data address breakpoint registers are 32-bit registers. The instruction
breakpoint causes a break before execution of the target instruction. The data breakpoint causes a
break after the memory access has been issued.
In this section Modified Virtual Address (MVA) refers to the virtual address ORed with the PID.
Refer to
Section 7.2.13, "Register 13: Process ID" on page 7-91
processor does not OR the PID with the specified breakpoint address prior to doing address
comparison. This must be done by the programmer and written to the breakpoint register as the
MVA. This applies to data and instruction breakpoints.
9.6.1
Instruction Breakpoints
The Debug architecture defines two instruction breakpoint registers (IBCR0 and IBCR1). The
format of these registers is shown in
Register
(IBCRx)". In ARM mode, the upper 30 bits contain a word aligned MVA to break on. In
Thumb mode, the upper 31 bits contain a half-word aligned MVA to break on. In both modes, bit 0
enables and disables that instruction breakpoint register. Enabling instruction breakpoints while
debug is globally disabled (DCSR.ge=0) may result in unpredictable behavior.
Table 9-5.
Instruction Breakpoint Address and Control Register (IBCRx)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: unpredictable address, disabled
Bits
31:1
0
An instruction breakpoint will generate a debug exception before the instruction at the address
specified in the ICBR executes. When an instruction breakpoint occurs, the processor sets the
DBCR.moe bits to 0b001.
Software must disable the breakpoint before exiting the handler. This allows the breakpointed
instruction to execute after the exception is handled.
Single step execution is accomplished using the instruction breakpoint registers and must be
completely handled in software (either on the host or by the debug handler).
130
Table 9-5, "Instruction Breakpoint Address and Control
Access
Read / Write
Read / Write
January, 2004
for more details on the PID. The
IBCRx
Description
Instruction Breakpoint MVA
in ARM* mode, IBCRx[1] is ignored
IBCRx Enable (E) -
0 = Breakpoint disabled
1 = Breakpoint enabled
8
7
6
5
4
3
2
1
0
E
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