Intel XScale Core Developer's Manual page 4

Intel XScale® Core Developer's Manual
Contents
3.2.2.2
3.2.2.3
3.2.2.4
3.2.2.5
3.2.2.6
3.2.3 Exceptions ............................................................................................................. 40
3.3 Interaction of the MMU, Instruction Cache, and Data Cache ............................................. 41
3.4 Control ................................................................................................................................ 42
3.4.1 Invalidate (Flush) Operation .................................................................................. 42
3.4.2 Enabling/Disabling ................................................................................................. 42
3.4.3 Locking Entries ...................................................................................................... 43
3.4.4 Round-Robin Replacement Algorithm ................................................................... 45
4 Instruction Cache........................................................................................................................... 47
4.1 Overview............................................................................................................................. 47
4.2 Operation ............................................................................................................................ 48
4.2.1 Operation When Instruction Cache is Enabled...................................................... 48
4.2.2 Operation When The Instruction Cache Is Disabled.............................................. 48
4.2.3 Fetch Policy ........................................................................................................... 49
4.2.4 Round-Robin Replacement Algorithm ................................................................... 49
4.2.5 Parity Protection .................................................................................................... 50
4.2.6 Instruction Fetch Latency....................................................................................... 51
4.2.7 Instruction Cache Coherency ................................................................................ 51
4.3 Instruction Cache Control ................................................................................................... 52
4.3.1 Instruction Cache State at RESET ........................................................................ 52
4.3.2 Enabling/Disabling ................................................................................................. 52
4.3.3 Invalidating the Instruction Cache.......................................................................... 53
4.3.4 Locking Instructions in the Instruction Cache ........................................................ 54
4.3.5 Unlocking Instructions in the Instruction Cache..................................................... 55
5 Branch Target Buffer ..................................................................................................................... 57
5.1 Branch Target Buffer (BTB) Operation ............................................................................... 57
5.1.1 Reset ..................................................................................................................... 58
5.1.2 Update Policy......................................................................................................... 58
5.2 BTB Control ........................................................................................................................ 59
5.2.1 Disabling/Enabling ................................................................................................. 59
5.2.2 Invalidation............................................................................................................. 59
6 Data Cache.................................................................................................................................... 61
6.1 Overviews ........................................................................................................................... 61
6.1.1 Data Cache Overview............................................................................................ 61
6.1.2 Mini-Data Cache Overview .................................................................................... 63
6.1.3 Write Buffer and Fill Buffer Overview..................................................................... 64
6.2 Data Cache and Mini-Data Cache Operation ..................................................................... 65
6.2.1 Operation When Caching is Enabled..................................................................... 65
6.2.2 Operation When Data Caching is Disabled ........................................................... 65
6.2.3 Cache Policies ....................................................................................................... 65
6.2.3.1
6.2.3.2
6.2.3.3
6.2.3.4
4
Cacheable (C), Bufferable (B), and eXtension (X) Bits.......................... 38
Instruction Cache ................................................................................... 38
Data Cache and Write Buffer ................................................................. 39
Details on Data Cache and Write Buffer Behavior................................. 40
Memory Operation Ordering .................................................................. 40
Cacheability ........................................................................................... 65
Read Miss Policy ................................................................................... 66
Write Miss Policy.................................................................................... 67
Write-Back Versus Write-Through ......................................................... 67
January, 2004 Developer's Manual