Data Aborts; Encoding Of Fault Status For Data Aborts - Intel XScale Core Developer's Manual

Intel XScale® Core Developer's Manual
Programming Model
2.3.4.4

Data Aborts

Two types of data aborts exist in the Intel XScale
abort is defined as one where R14_ABORT always contains the PC (+8) of the instruction that
caused the exception. An imprecise abort is one where R14_ABORT contains the PC (+4) of the
next instruction to execute and not the address of the instruction that caused the abort. In other
words, instruction execution will have advanced beyond the instruction that caused the data abort.
On the core, precise data aborts are recoverable and imprecise data aborts are not recoverable.
Precise Data Aborts
•
A lock abort is a precise data abort; the extended Status field of the Fault Status Register is set
to 0xb10100. This abort occurs when a lock operation directed to the MMU (instruction or
data) or instruction cache causes an exception, due to either a translation fault, access
permission fault or external bus fault.
The Fault Address Register is undefined and R14_ABORT is the address of the aborted
instruction + 8.
•
A data MMU abort is precise. These are due to an alignment fault, translation fault, domain
fault, permission fault or external data abort on an MMU translation. The status field is set to a
predetermined ARM definition which is shown in
Data Aborts" on page
The Fault Address Register is set to the effective data address of the instruction and
R14_ABORT is the address of the aborted instruction + 8.
Table 2-14.

Encoding of Fault Status for Data Aborts

Priority
Highest Alignment
Lowest
a. All other encodings not listed in the table are reserved.
Imprecise data aborts
•
A data cache parity error is imprecise; the extended Status field of the Fault Status Register is
set to 0xb11000.
•
All external data aborts except for those generated on a data MMU translation are imprecise.
The Fault Address Register for all imprecise data aborts is undefined and R14_ABORT is the
address of the next instruction to execute + 4, which is the same for both ARM and Thumb mode.
34
2-34.
Sources
External Abort on Translation
Translation
Domain
Permission
Lock Abort
This data abort occurs on an MMU lock operation (data or
instruction TLB) or on an Instruction Cache lock operation.
Imprecise External Data Abort
Data Cache Parity Error Exception
January, 2004
®
core: precise and imprecise. A precise data
Table 2-14, "Encoding of Fault Status for
FS[10,3:0]
0b000x1
First level 0b01100
Second level 0b01110
Section 0b00101
Page 0b00111
Section 0b01001
Page 0b01011
Section 0b01101
Page 0b01111
0b10100
0b10110
0b11000
a
Domain FAR
invalid valid
invalid valid
valid valid
invalid valid
valid valid
valid valid
valid valid
valid valid
valid valid
invalid invalid
invalid invalid
invalid invalid
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