Software Debug Registers; Accessing The Debug Registers - Intel XScale Core Developer's Manual

7.3.3

Software Debug Registers

Software debug is supported by address breakpoint registers (Coprocessor 15, register 14), serial
communication over the JTAG interface and a trace buffer. Registers 8, 9 and 14 are used for the
serial interface, register 10 is for general control and registers 11 through 13 support a 256 entry
trace buffer. These registers are explained in more detail in
Opcode_2 and CRm should be zero.
Table 7-26.

Accessing the Debug Registers

Transmit Debug Register (TX)
Receive Debug Register (RX)
Debug Control and Status Register (DBGCSR)
Trace Buffer Register (TBREG)
Checkpoint 0 Register (CHKPT0)
Checkpoint 1 Register (CHKPT1)
Transmit and Receive Debug Control Register
Developer's Manual
Function
January, 2004
Intel XScale® Core Developer's Manual
Chapter 9, "Software
CRn (Register #)
0b1000 MCR p14, 0, Rd, c8, c0, 0
0b1001 MRC p14, 0, Rd, c9, c0, 0
MCR p14, 0, Rd, c10, c0, 0
0b1010
MRC p14, 0, Rd, c10, c0, 0
0b1011 MRC p14, 0, Rd, c11, c0, 0
MCR p14, 0, Rd, c12, c0, 0
0b1100
MRC p14, 0, Rd, c12, c0, 0
MCR p14, 0, Rd, c13, c0, 0
0b1101
MRC p14, 0, Rd, c13, c0, 0
MCR p14, 0, Rd, c14, c0, 0
0b1110
MRC p14, 0, Rd, c14, c0, 0
Configuration
Debug".
Instruction
99