Mrc/Mcr Format - Intel XScale Core Developer's Manual

Intel XScale® Core Developer's Manual
Configuration
The format of MRC and MCR is shown in
The Intel XScale
cp_num. CP0 supports instructions specific for DSP and is described in
Model." Refer to the Intel XScale
specification to find out what other coprocessors, if any, are supported in the ASSP.
Unless otherwise noted, unused bits in coprocessor registers have unpredictable values when read.
For compatibility with future implementations, software should not rely on the values in those bits.
Table 7-1.

MRC/MCR Format

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
cond
Bits
31:28
23:21
20
19:16
15:12
11:8
7:5
3:0
78
®
core implements CP15, CP14 and CP0 coprocessors, which is specified by
®
core implementation option section of the ASSP architecture
1 1 1 0 n
opcode_1
Description
cond - ARM* condition codes
opcode_1 - Reserved
n - Read or write coprocessor register
0 = MCR
1 = MRC
CRn - specifies which coprocessor register
Rd - General Purpose Register, R0..R15
cp_num - coprocessor number
opcode_2 - Function bits
CRm - Function bits
January, 2004
Table 7-1.
CRn Rd cp_num
-
Should be programmed to zero for future
compatibility
-
-
-
The Intel XScale
coprocessors:
0b1111 = CP15
0b1110 = CP14
0x0000 = CP0
NOTE: Refer to the Intel XScale
implementation option section of the
ASSP architecture specification to see
if there are any other coprocessors
defined by the ASSP.
This field should be programmed to zero for
future compatibility unless a value has been
specified in the command.
This field should be programmed to zero for
future compatibility unless a value has been
specified in the command.
Chapter 2, "Programming
8 7 6 5 4 3 2 1
1 CRm
opcode_2
Notes
®
core defines three
®
core
Developer's Manual
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