Memory Management; Overview - Intel XScale Core Developer's Manual

Memory Management

This chapter describes the memory management unit implemented in the Intel XScale
3.1

Overview

The Intel XScale
in the ARM Architecture Reference Manual. To accelerate virtual to physical address translation,
the core uses both an instruction Translation Look-aside Buffer (TLB) and a data TLB to cache the
latest translations. Each TLB holds 32 entries and is fully-associative. Not only do the TLBs
contain the translated addresses, but also the access rights for memory references.
If an instruction or data TLB miss occurs, a hardware translation-table-walking mechanism is
invoked to translate the virtual address to a physical address. Once translated, the physical address is
placed in the TLB along with the access rights and attributes of the page or section. These translations
can also be locked down in either TLB to guarantee the performance of critical routines.
The Intel XScale
memory:
•
cacheable
•
bufferable
•
line allocate policy
•
write policy
•
I/O
•
mini Data Cache
•
Coalescing
•
an ASSP definable attribute - P bit (Refer to the Intel XScale
the ASSP architecture specification for more information.)
See Section 3.2.2, "Memory Attributes" on page 3-38
Section 2.3.2, "New Page Attributes" on page 2-29
mapped in the MMU descriptors.
Note: The virtual address with which the TLBs are accessed may be remapped by the PID register. See
Section 7.2.13, "Register 13: Process ID" on page 7-91
Developer's Manual
®
core implements the Memory Management Unit (MMU) Architecture specified
®
core allows system software to associate various attributes with regions of
January, 2004
Intel XScale® Core Developer's Manual
Memory Management
®
core implementation section of
for a description of page attributes and
to find out where these attributes have been
for a description of the PID register.
3
®
core.
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