Page 1 ® Intel Xeon™ Processor with ® 512 KB L2 Cache and Intel E7500 Chipset Platform Design Guide March 2002 Document Number: 298649-002...
Page 2 The Intel ® E7500 chipset and processors in the Intel ® Xeon processor family may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Page 3: Table Of Contents
82870P2 P64H2) ....22 1.3.3 Bandwidth Summary ................23 1.3.4 System Configurations ...............23 Component Quadrant Layout ................25 Intel® Xeon™ Processor with 512 KB L2 Cache Quadrant Layout ....26 Intel® E7500 MCH Quadrant Layout..............27 ® Intel ICH3-S Quadrant Layout ................28 ® Intel 82870P2 P64H2 Quadrant Layout ............29 Platform Stack-Up and Component Placement Overview .......31...
Page 4 Hub Interface 1.5 Generation/Distribution of Reference Voltages ..90 7.3.3 Hub Interface 1.5 Resistive Compensation ........91 7.3.4 Hub Interface 1.5 Decoupling Guidelines........... 92 ® Intel 82870P2 (P64H2) ..................93 PCI/PCI-X Design Guidelines ................93 8.1.1 PCI/PCI-X Routing Requirements (No Hot Plug) ....... 94 8.1.2...
Page 5 Manually-Operated Retention Latch Sensor.......101 8.2.2.2 Optional Attention Button............102 8.2.3 LED Indicator Outputs ..............102 ® 8.2.4 Disabling/Enabling an Intel P64H2 Hot Plug Controller....103 8.2.4.1 Hot Plug Strapping Options ..........103 8.2.4.2 Hot Plug Registers’ Visibility ..........103 8.2.5 Single Slot Parallel Mode ..............103 8.2.5.1...
Page 6 Board Design ..............140 9.7.2.7 Common Physical Layout Issues ........140 ® 9.7.3 Intel 82562ET/EM Guidelines ............142 ® 9.7.3.1 Guidelines for Intel 82562ET/EM Component Placement 142 9.7.3.2 Crystals and Oscillators ............142 ® 9.7.3.3 Intel 82562ET/EM Termination Resistors......143 9.7.4 Critical Dimensions................
Page 7 Hub Interface (1.2 V Power Plane)...........178 12.3.5 Filter Specifications (1.2V Power Plane) ..........179 12.3.6 MCH Power Sequencing Requirement ..........180 ® 12.4 Intel ICH3-S Power Delivery Guidelines ............181 12.4.1 1.8 V/3.3 V Power Sequencing ............181 12.4.2 3.3V/V5REF Sequencing ..............182 ® 12.4.3 Intel ICH3-S Power Rails..............183...
Page 8 12.5 Intel® P64H2 Power Requirements ..............185 12.5.1 Intel® P64H2 Current Requirements ..........185 12.5.2 Intel® P64H2 Decoupling Requirements ......... 185 12.5.3 PCIRST# Implementation..............186 12.5.4 P64H2 Power Sequencing Requirement.......... 186 Schematic Checklist ..................... 187 13.1 Processor Schematic Checklist................. 187 13.2...
Page 9 Figures Example Intel® Xeon™ Processor with 512 KB L2 Cache / Intel® E7500 Chipset Based System Configuration23 Intel® Xeon™ Processor with 512 KB L2 Cache Quadrant Layout (Top View) ..26 ® Intel E7500 MCH Quadrant Layout (Top View)..........27 ® Intel ICH3-S Quadrant Layout (Top View) ............28...
Page 10 Connection Requirements for Secondary IDE Connector......... 122 Example Speaker Circuit................... 123 PCI Bus Layout Example .................. 124 Suggested USB Downstream Power Connection ..........126 Intel® ICH3-S SMBus / SMLink Interface ............127 Unified VCC_3.3 Architecture ................128 RTCX1 and SUSCLK Relationship ..............128 9-10 RTC External Circuitry ..................
Page 11 9-20 Critical Dimensions for Component Placement..........143 9-21 Termination Plane .....................145 11-1 Spread Spectrum Modulation Profile..............151 11-2 Impact of Spread Spectrum Clocking on Radiated Emissions ......151 11-3 Cancellation of H-fields Through Inverse Currents ...........152 11-4 Conceptual Processor Ground Frame...............154 11-5 Retention Mechanism Outline and Ground Pad Detail........155 11-6 Retention Mechanism Placement and Keep-Out Overview ......156 11-7...
Page 12 Tables Reference Documents ..................15 Intel® Xeon™ Processor with 512 KB L2 Cache Feature Set Overview .... 20 Platform Maximum Bandwidth Summary ............23 Assumptions for System Placement Example ............ 31 E7500 Chipset Customer Reference Board Requirements ........ 33 CK408B Clock Groups ..................35 Platform System Clock-Reference ..............
Page 13 12-4 Component Recommendation—Capacitor............171 12-5 Processor High-Frequency Capacitance Recommendations......173 12-6 Processor Bulk Capacitance Recommendations ..........175 12-7 Various Component Models Used at Intel (Not Vendor Specifications) ....177 12-8 ICH3-S Power Rail Terminology ...............183 ® 12-9 Intel ICH3-S Decoupling Recommendations...........184 12-10 Intel® P64H2 Max Sustained Currents .............185 12-11 Decoupling Capacitor Recommendations ............185...
Page 14: Revision History
Revision History Revision Description Date -001 Initial Release. February 2002 Changed: Section 6.3; DDR Command Clock Figure Notes Added: Section 12.5.4; New P64H2 Power Sequencing -002 March 2002 Requirement Updated Schematics to reflect changes identified above. Design Guide...
Page 15: Introduction
Note that the guidelines recommended in this document are based on experience and simulation work done at Intel while developing Intel Xeon processor with 512 KB L2 cache / E7500 chipset- based systems. This work is ongoing, and the recommendations are subject to change.
Page 16 Xeon™ Processor with 512 KB L2 Cache Mechanical Model in ProE* http://developer.intel.com/design/ Format Xeon/devtools/ ® Intel Xeon™ Processor with 512 KB L2 Cache at 1.80 GHz, 2 GHz, and http://developer.intel.com/design/ 2.20 GHz Datasheet Xeon/datashts/298642.htm ® AP-728 Intel ICH Family Real Time Clock (RTC) Accuracy and http://developer.intel.com/design/...
Page 17: Conventions And Terminology
Asynchronous GTL+ Xeon processors do not utilize CMOS voltage levels on any signals that connect to the processor. As a result, legacy input signals such as A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#, and STPCLK# utilize GTL+ input buffers.
Page 18 Introduction Convention/Terminology Description Flight Time Flight time is a term in the timing equation that includes the signal propagation delay, any effects the system has on the Tco of the driver, plus any adjustments to the signal at the receiver needed to guarantee the setup time of the receiver. More precisely, flight time is defined as: •...
Page 19: System Overview
System Overview The E7500 chipset is Intel’s first generation server chipset designed for use with the Xeon processor. The architecture of the chipset provides the performance and feature-set required for dual-processor based severs in the entry-level and mid-range, front-end and general-purpose server market segments.
Page 20: Intel® Xeon™ Processor With 512 Kb L2 Cache
Intel NetBurst™ microarchitecture. The Xeon processor delivers performance levels that are significantly higher than previous generations of IA- 32 processors. The E7500 chipset supports all speeds of the Intel Xeon processor with 512 KB L2 cache. ®...
Page 21: Intel® E7500 Chipset
Introduction ® 1.3.2 Intel E7500 Chipset ® The E7500 chipset consists of three major components: the Intel E7500 Memory Controller Hub ® (referred to throughout this document as the MCH), the Intel 82801CA I/O Controller Hub 3-S ® (hereafter referred to as ICH3-S), and the Intel 82870P2 PCI/ PCI-X 64-bit Hub 2 (abbreviated to P64H2).
Page 22: I/O Controller Hub 3 (Intel Ich3-S)
Introduction ® 1.3.2.2 I/O Controller Hub 3 (Intel ICH3-S) The I/O Controller Hub (ICH3-S) provides the legacy I/O subsystem for E7500 chipset-based platforms. Additionally, it integrates many advanced I/O functions. The ICH3-S includes the following features: • Provides HI1.5 Connection to MCH: —...
Page 23: Bandwidth Summary
Figure 1-1 illustrates an example E7500 chipset-based system configuration for server platforms using Xeon processors. ® ® Figure 1-1. Example Intel Xeon™ Processor with 512 KB L2 Cache / Intel E7500 Chipset Based System Configuration Processor Processor System Memory 200 MHz...
Page 24 Introduction This page is intentionally left blank. Design Guide...
Page 25: Component Quadrant Layout
Designers should use only the exact ball assignment to conduct routing analyses. Reference the following documents for exact ball assignment information. ® • Intel Xeon™ Processor with 512 KB L2 Cache at 1.80 GHz, 2 GHz, and 2.20 GHz Datasheet ® • Intel 82801CA I/O Controller Hub 3 (ICH3-S) Datasheet ®...
Page 26: Intel Xeon™ Processor With 512 Kb L2 Cache Quadrant Layout
Component Quadrant Layout ® Intel Xeon™ Processor with 512 KB L2 Cache Quadrant Layout ® Figure 2-1. Intel Xeon™ Processor with 512 KB L2 Cache Quadrant Layout (Top View) COMMON COMMON Async / ADDRESS CLOCK CLOCK JTAG CLOCKS DATA SMBus...
Page 27: Intel® E7500 Mch Quadrant Layout
Intel E7500 MCH Quadrant Layout ® Figure 2-2. Intel E7500 MCH Quadrant Layout (Top View) DDR A 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 HI_A–D...
Page 28: Intel ® Ich3-S Quadrant Layout
Component Quadrant Layout ® Intel ICH3-S Quadrant Layout ® Figure 2-3. Intel ICH3-S Quadrant Layout (Top View) Interface GPIO SMBus LPC/Firm Ware AC'97 VCC_1.8 EEPROM VCCSUS_1.8 HUB Interface VCC_3.3 GPIO VCCSUS_3.3 Misc. VCC SMBus Design Guide...
Page 29: Intel ® 82870P2 P64H2 Quadrant Layout
Component Quadrant Layout ® Intel 82870P2 P64H2 Quadrant Layout ® Figure 2-4. Intel P64H2 Quadrant Layout (Top View) Hub Interface IRQs Hot Plug VCC3.3 VCC1.8 VCC5REF PBIRQ PSTRB APIC PAIRQ MISC BPCLK SCLK/SDATA Design Guide...
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Page 31: Platform Stack-Up And Component Placement Overview
Platform Stack-Up and Component Placement Overview Platform Component Placement Figure 3-1 illustrates the component placement for the Intel Xeon processor with 512 KB L2 cache/Intel E7500 chipset-based customer reference board (E7500 CRB). Table 3-1 lists the assumptions used for the component placement. Refer to www.ssiforum.org for detailed information on the SSI (Server System Infrastructure) specification.
Page 32: Platform Stack-Up
Table 3-2 when designing their boards. Intel realizes numerous ways exist to achieve these targeted impedance tolerances; contact your board vendor for these specifics. Intel encourages platform designers to perform comprehensive simulation analysis to ensure all timing specifications are met. This is particularly important if a design deviates from the design guidelines provided.
Page 33: Intel® E7500 Chipset Customer Reference Board System Placement Example 32 3-2 8 Layer, 50 Ω Board With 5 Mil Traces
Platform Stack-Up and Component Placement Overview Figure 3-2. 8 Layer, 50 Ω Board with 5 mil Traces Layer 1 2.1 mil (1 oz + plating) Power Dielectric 9.6 mil Dielectric Layer 2 Signal Signal Signal 1.4 mil (1 oz) Core 5.2 mil Core Ground 1.4 mil (1 oz)
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Page 35: Platform Clock Routing Guidelines
Platform Clock Routing Guidelines Platform Clock Routing Guidelines To minimize jitter, improve routing, and reduce cost, E7500 chipset-based systems should use a single chip clock solution, the CK408B. In this configuration, the CK408B provides four, 100 MHz differential outputs pairs for all of the bus agents, including the ITP connector, and five, 66 MHz speed clocks that drive all I/O buses.
Page 36: Platform System Clock-Reference
Platform Clock Routing Guidelines Table 4-2. Platform System Clock-Reference Clock Group CK-408B Pin Component Component Pin Name Host_CLK CPU# Debug Port BCLK[0] Debug Port BCLK[1] CPU# Processor 0 BCLK[0] Processor 0 BCLK[1] CPU# Processor 1 BCLK[0] Processor 1 BCLK[1] CPU# HCLKINP HCLKINN CLK66...
Page 37: Intel® E7500 Chipset-Based System Clocking Diagram
Platform Clock Routing Guidelines ® Figure 4-1. Intel E7500 Chipset-Based System Clocking Diagram CK408B Channel A Host_CLK Processor CPU / CPU# (4) DIMMclk (x4 pr.) Processor Channel B CLK66 DIMMclk (x4 pr.) 66BUF (5) CLK14 ® Intel ICH-S REF0 (1)
Page 38: Clock Groups
Platform Clock Routing Guidelines Clock Groups 4.1.1 HOST_CLK Clock Group 4.1.1.1 HOST_CLK Clock Topology The clock synthesizer provides four sets of 100 MHz differential clock outputs. The 100 MHz differential clocks are driven to the Processors, the MCH, and the processors’ debug port as shown Figure 4-1.
Page 39: Host_Clk[1:0]# Routing Guidelines
Platform Clock Routing Guidelines Table 4-3. HOST_CLK[1:0]# Routing Guidelines Layout Guideline Value Illustration Notes 300 ps total budget: Figure 4-2 HOST_CLK Skew between Agents 150 ps for clock driver 1,2,3,4 Figure 4-3 150 ps for interconnect Trace Width 5 mils Figure 4-4 Differential Pair Spacing 20 –...
Page 40: Clock Skew As Measured From Agent To Agent
Platform Clock Routing Guidelines 4. Skew measured at the load between any two-bus agents. Measured at the crossing point. 5. Edge to edge spacing between the two traces of any differential pair. Uniform spacing should be maintained along the entire length of the trace. 6.
Page 41: Host_Clk General Routing Guidelines
Platform Clock Routing Guidelines 4.1.1.2 HOST_CLK General Routing Guidelines • When routing the 100 MHz differential clocks, do not split up the two halves of a differential clock pair between layers. Route to all agents on the same physical routing layer referenced to ground.
Page 42: Clk66 Clock Group
In the CLK66 clock group, the driver is the clock synthesizer 66 MHz clock output buffer, and the receiver is the 66 MHz clock input buffer at the MCH, ICH3-S, and P64H2. Figure 4-6. Topology for CLK66 Clock MCH, ® Driver Intel ICH3-S, ® Intel P64H2 Table 4-4. CLK66 Routing Guidelines Parameters...
Page 43: Clk66 Skew Requirements
Figure 4-7. Clock Skew Requirements Total Length = X 43 Ω CK408B Total Length = X - 0.34" ® Intel P64H2 43 Ω Resistor must be within 500 mils of CK408B NOTES: 1. All lengths must be matched within 100 mils of target length.
Page 44: Example Of Adding A Single Connector
Figure 4-8. Example of Adding a Single Connector Total Length = X 43 Ω CK408B Motherboard Trace Length = X - 0.34" - 0.60" - Z ® Intel = X - 0.94" - Z P64H2 43 Ω Resistor must be within 500 mils of CK408B NOTES: 1.
Page 45: Clk33_Ich3-S Clock
In the CLK33_ICH3-S case, the driver is the clock synthesizer 33 MHz clock output buffer, and the receiver is the 33 MHz clock input buffer at the ICH3-S. Figure 4-10. Topology for CLK33_ICH3-S Clock ® Intel ICH3-S Driver Table 4-5. CLK33_ICH3-S Routing Guidelines Parameter...
Page 46: Clk33 Clock Group
Platform Clock Routing Guidelines 4.1.4 CLK33 Clock Group For the CLK33 clock group, the driver is the clock synthesizer 33 MHz clock output buffer, and the receiver is the 33 MHz clock input buffer at the PCI devices on the PCI cards. Figure 4-11.
Page 47: Topology For Clk33 To Pci Slot
Platform Clock Routing Guidelines Figure 4-12. Topology for CLK33 to PCI Slot Trace On PCI Card PCI Device Clock Driver Connector Table 4-7. CLK33 Routing Guidelines for PCI Slot Parameter Routing Guidelines Clock Group CLK33 Topology Point-to-Point Reference Plane Ground referenced (contiguous over entire length) 50 Ω...
Page 48: Clk14 Clock Group
The driver in the CLK14 clock group is the clock synthesizer 14.318 MHz clock output buffer, and the receiver is the 14.318 MHz clock input buffer at the ICH3-S, SIO and LPC. Figure 4-13. Topology for CLK14 ® Clock Intel ICH3-S Driver SIO, and LPC Table 4-8. CLK14 Routing Guidelines...
Page 49: Usbclk Clock Group
USB clock input buffer at the ICH3-S. Note that this clock is asynchronous to any other clock on the board. Figure 4-14. Topology for USB_CLK Clock ® Intel ICH3-S Driver Table 4-9. USBCLK Routing Guidelines Parameter Routing Guideline...
Page 50: Clock Driver Decoupling
Platform Clock Routing Guidelines Clock Driver Decoupling The decoupling requirements for a CK408B compliant clock synthesizer are as follows: • One, 22 µF polarized (decoupling) capacitor placed close to the VDD generation circuitry. • Eleven, 0.1 µF high-frequency decoupling capacitors placed close to the VDD pins on the clock driver.
Page 51: Clock Driver Power Delivery
Platform Clock Routing Guidelines Clock Driver Power Delivery Designers must take special care to provide a quiet VDDA supply to the Ref VDD, VDDA and the 48 MHz VDD. These VDDA signals are especially sensitive to switching noise induced by the other VDDs on the clock chip.
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Page 53: System Bus Routing Guidelines
If the signal is not connected, it must be pulled to the appropriate voltage level through a 1 k Ω ± 5% resistor. 2. Xeon processors use only BR0# and BR1#. 3. These signals are ‘wired-OR’ signals and may be driven simultaneously by multiple agents. For further details...
Page 54: Dual Processor System Bus Topology
Use this as a quick reference only. The following sections provide more detailed information for each parameter. Intel strongly recommends simulation of all signals to ensure the design meets setup and hold times.
Page 55: System Bus Routing Summary
System Bus Routing Guidelines Table 5-2. System Bus Routing Summary Parameter Platform Routing Guidelines Trace Width/Spacing 5/15 mils. 2X and 4X Signal Group Line 3.0" – 10.1" pin-to-pin. Lengths Total bus length must not exceed 20.2". (Agent-to-Agent Length) Trace lengths must be balanced ± 25 mils with respect to the strobe between agents to compensate for the stub created by the processor package.
Page 56: Routing Guidelines For The Agtl+ Source Synchronous 2X And 4X Groups
System Bus Routing Guidelines Routing Guidelines for the AGTL+ Source Synchronous 2X and 4X Groups The 4X group of signals uses four times the frequency of the base clock, or 400 MHz. The 2X group uses twice the frequency of the base clock, or 200 MHz. The 2X and 4X signals are listed in Table 5-3.
Page 57: Trace Length Matching For The Dual Processor System Bus
The package trace lengths for the MCH are available in the Intel E7500 Chipset Memory Controller Hub (MCH) Datasheet. The package trace lengths for the Intel Xeon processor with 512 ® KB L2 cache are available in the matching spreadsheet contained in the Intel Xeon™...
Page 58: Routing Guidelines For Common Clock Signals
BINIT#, and BNR#. These signals differ from the other system bus signals in that more than one agent can be driving the signal at the same time. However, Intel recommends that special attention be given to the routing of these signals in adherence to the layout guidelines presented in Table 5-2.
Page 59: Reset# Topology
System Bus Routing Guidelines 5.2.2 RESET# Topology Since the processor does not contain on-die termination for the RESET# input signal, these additional layout guidelines for the RESET# signal are required. The baseboard trace length from Processor 0's pin to the termination resistor should be 0 to 1 inch.Follow the same routing guidelines given for common clock signals listed above in this same section.
Page 60: Asynchronous Gtl+ Signals Driven By The Processor
Baseboard Management Controller) and may need voltage translation logic, depending on the motherboard receiver logic devices used. Do not route a stub when routing to the processors. Figure 5-4. Topology for Asynchronous GTL+ Signals Driven by the Processor VCC_CPU VCC_CPU ® Intel Processor 0 Processor 1 Ω Ω ± 5% ±...
Page 61: Proper Thermtrip# Usage
CPUSLP#, SMI# and STPCLK#. Do not route a stub when routing to the processors. Figure 5-6. Topology for Asynchronous GTL+ Signals Driven by the Chipset VCC_CPU Processor 0 Processor 1 ® Intel Ω ± 5% ICH3-S 0.1" – 3.0" 0.1" – 9.0"...
Page 62: Proper Power Good Usage
5-7. You may choose to isolate PWRGOOD for each voltage regulator and processor pair in order to recognize individual voltage regulator failures. Figure 5-7. Topology for PWRGOOD (CPUPWRGOOD) VCC_CPU Processor 0 Processor 1 ® Intel Ω ± 5% ICH3-S 0.1" – 3.0" 0.1" – 9.0" 0.1" – 9.0"...
Page 63: Vid[4:0]
® Intel Xeon™ Processor with 512 KB L2 Cache at 1.80 GHz, 2 GHz, and 2.20 GHz Datasheet for details on the Xeon processor implementation and addressing scheme. Connect the SM_ALERT#, SM_CLK, and SM_DAT signals to the SMBus controller in adherence to the System Management Bus (SMBus) Specification, Version 1.1.
Page 64: System Bus Comp Routing Guidelines
Processor- Processor- Processor-to- Impedance BR1# to to-Processor to-R Stub Stub ® Intel 50 Ω 50 Ω ± 5% 50 Ω ± 5% 3.0 – 10.0” 15.7” max 1” max 3” max 5.3.7 ODTEN Signal Routing Guidelines Processor 0, the end processor in a dual processor system, must have its on-die termination enabled.
Page 65: Testhi[6:0] Routing Guidelines
System Bus Routing Guidelines 5.3.8 TESTHI[6:0] Routing Guidelines All TESTHI[6:0] pins must be connected to VCC_CPU via pull-up resistors with a termination value within 20% of the signal impedance (50 Ω ± 20%). TESTHI[3:0] may all be tied together and pulled up to VCC_CPU with a single, 50 Ω...
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Page 67: Memory Interface Routing Guidelines
Miscellaneous. Table 6-1 summarizes the signal groupings. The MCH contains two complete ® sets of these signals, one set per channel. Refer to the Intel E7500 Chipset Memory Controller Hub (MCH) Datasheet for details on the signals listed in Table 6-1.
Page 68: Ddr Overview
Clock routing and Chip Select routing documented in Figure 6-2 Figure 6-1. This addressing must be maintained to be compliant with the reference BIOS code supplied by Intel. Designs with fewer than 3 DIMMs should follow the pattern shown in Figure 6-2 Figure 6-1.
Page 69: Trace Width And Spacing For All Ddr Signals Except Cmdclk/Cmdclk
Memory Interface Routing Guidelines The DDR interface requires a nominal impedance (Zo) of 50 Ω ± 10%. Using the recommended stackup, all routing layers yield 50 Ω nominal impedance when using 5 mil wide traces. Route all DDR signals 5/15 (5 mils wide with 15 mil spacing) as shown in Figure 6-3 with the exception of CKE, CMDCLK[3:0], and CMDCLK[3:0]#.
Page 70: Source Synchronous Signal Group
Memory Interface Routing Guidelines Source Synchronous Signal Group The MCH source synchronous signals are divided into groups consisting of data bits (DQ) and check bits (CB). An associated strobe (DQS) exists for each DQ and CB group, as shown in Table 6-2.
Page 71: Source Synchronous Topology
Memory Interface Routing Guidelines Table 6-3. Source Synchronous Signal Group Routing Guidelines ® Parameter Intel E7500 Reference Signal Group DQ[63:0], CB[7:0], DQS[17:0] Topology Daisy Chain Figure 6-4 Reference Plane Ground Figure 6-3 50 Ω ± 10% MCH to Rtt (Zo)
Page 72: Trace Length Matching Requirements For Source Synchronous Routing
Memory Interface Routing Guidelines Figure 6-5. Trace Length Matching Requirements for Source Synchronous Routing DIMM Shortest Strobe (DQS) = X Shortest Data (DQ) = Y – 100 mils NOTES: 1. The DIMM displayed represents any DIMM. All DIMMs must be length matched within the specified distance. A simple method to do this is to length match the MCH to the first DIMM within the specified tolerance and then match all the signals DIMM to DIMM.
Page 73: Command Clock Routing
CMDCLK0 and CMDCLK0#) must be length matched to each other within ± 2 mils. Excluding breakout, the maximum recommended layer changes is one. Ensure that the reference plane does not change when switching layer. Table 6-4. Command Clock Pair Routing Guidelines ® Parameter Intel E7500 Reference Signal Group CMDCLK[3:0], CMDCLK[3:0]# Topology...
Page 74: Trace Width/Spacing For Cmdclk/Cmdclk# Routing
5 mil 20 mil 5 mil NOTE: The Intel E7500 MCH may also use a 5 mil space between CMDCLK complements. Figure 6-9. Length Matching Requirements for Source Clocked Signal, CKE, and CS[7:0]# DIMM Longest CTRL length = x + 2.0"...
Page 75: Source Clocked Signal Group Routing
MCH to the DIMM that CMDCLK0/CMDCLK0# is routed to should be 3 inches ± 2.0 inches. Table 6-5. Source Clocked Signal Group Routing Guidelines ® Parameter Intel E7500 Reference Signal Group RAS#, CAS#, WE#, MA[12:0], BA[1:0] Topology...
Page 76: Chip Select Routing
The E7500 chip selects for each DIMM must be length matched to the corresponding clock within ± 2.0 inches and require parallel termination resistors (Rtt) to DDR VTERM, placed within 3 inches of their associated connector. Table 6-6. Chip Select Routing Guidelines ® Parameter Intel E7500 Reference Signal Group CS[7:0]# Topology...
Page 77: Clock Enable Routing
The CKE signal requires a parallel termination resistor (Rtt) to DDR VTERM placed as close to the last DIMM connector as possible. Table 6-7. Clock Enable Routing Guidelines ® Parameter Intel E7500 Reference Signal Group Topology Daisy Chain with Stubs...
Page 78: Enable Signal (Rcven#)
Memory Interface Routing Guidelines Enable Signal (RCVEN#) The MCH uses the “receive enable” (RCVEN#) signal to determine the approximate DIMM round-trip flight time (command flight + data flight). Two pins exist on the MCH to facilitate the use of RCVEN#: RCVENOUT# and RCVENIN#. RCVENOUT# is an output of the MCH, and RCVENIN# is an input to the MCH.
Page 79: Miscellaneous Signals
Memory Interface Routing Guidelines Miscellaneous Signals The MCH uses a compensation signal to adjust buffer characteristics and output voltage swing over temperature, process, and voltage skew. Calibration is done periodically by sampling the DDRCOMP, DDRCVOH, and DDRCVOL pins on the MCH. Connect DDRCOMP to the DDR termination voltage (1.25 V) through a 6.81 Ω...
Page 80: Ddr Reference Voltage
Memory Interface Routing Guidelines DDR Reference Voltage The DDR system memory reference voltage (VREF) is used by the DRAM devices and the MCH to determine the logic level being driven on the data, strobe, and control signals. VREF of the receiving device must track changes in VTT to maximize DDR interface margin.
Page 81: Ddr Signal Termination
Memory Interface Routing Guidelines 6.10 DDR Signal Termination Place a 1.25 V termination plane on the top layer just beyond the DIMM connector furthest from the MCH on each channel, as shown in Figure 6-18. The VTERM island must be at least 50 mils wide.
Page 82: Decoupling Requirements
Memory Interface Routing Guidelines 6.11 Decoupling Requirements Decouple the DIMM connectors as shown in Figure 6-19. Place six ceramic 0.1 µF (0603) capacitors between adjacent DIMM connectors. Place ten Tantalum 100 µF capacitors per channel around the DIMM connectors, keeping them within 0.5" of the edge of the DIMM connectors. Again, be sure to implement two vias per capacitor (ceramic and tantalum) to the internal ground plane.
Page 83: Hub Interface
Note that throughout the document, the ‘x’ part of the MCH signal has been dropped for simplicity. Figure 7-1. Signal Naming Convention on Both Sides of the Hub Interfaces ® Intel P64H2 HI2.0 PUSTRBS...
Page 84: Hub Interface 2.0 Implementation
7-2. The general routing guidelines for the Hub Interface 2.0 signals are given in Table 7-3. Table 7-2. Hub Interface 2.0 Signal Groups Signal Group ® Intel P64H2 Common Clock Signals HI[19:16]_x HI[19:16] HI[21:20]_x, HI[15:0]_x, HI[21:20],HI[15:0], Source Synchronous Signals PSTRBF, PSTRBS, PUSTRBF,...
Page 85 Hub Interface The Hub Interface signals must be routed directly from the MCH to P64H2 with all signals referenced to ground. Maintain a consistent ground reference plane at all times. In addition, route all signals within a data group (consisting of nine bits of data and a pair of strobes) on the same layer and reference them to the same ground plane.
Page 86: Hub Interface 2.0 Length Matching
3 inches to (11-Y) inches, where Y is the riser card trace length. The riser must be built to not exceed the maximum trace length with the motherboard routed length. Figure 7-3. Hub Interface 2.0 Routing Guidelines for Device Down Solutions 3" - 20" PSTRBF PSTRBS ® Intel PUSTRBF P64H2 PUSTRBS HI_[21:0] CLK66 CLK66...
Page 87: Hub Interface 2.0 Generation/Distribution Of Reference Voltages
Hub Interface Figure 7-4. Hub Interface 2.0 Routing Guidelines for Hub Interface Connector Solutions 3" - 14" PSTRBF PSTRBS PUSTRBF PUSTRBF HI_[21:0] CLK66 CLK66 CK408B NOTE: The 14 inch maximum length allows for a single connector and 3 inch adaptor card trace length. The PCI connector is an equivalent 3 inch electrical length.
Page 88: Hub Interface 2.0 Resistive Compensation
Hub Interface Figure 7-5. Hub Interface 2.0 with Locally Generated Voltage Divider Circuit 1.2 V 1.8 V 0.8 V ® Intel P64H2 0.8 V HISWNG_x HI_VSWING HI_VREF HIVREF_x 0.35 V 0.35 V The resistor values R1, R2, R3, R4, R5, and R6 must be rated at ± 1% tolerance. The selected resistor values must also ensure that the reference voltage and reference swing voltage tolerance are maintained over the input leakage specification.
Page 89: Hub Interface 2.0 Decoupling Guidelines
Hub Interface 1.0 mode, HI_STBF and HI_STBS are called HI_STB# and HI_STB, respectively. Figure 7-7. 8-Bit Hub Interface 1.5 Routing HI_STBF HI_STBS ® Intel HI[11:0] ICH3-S CLK66 CLK66 Synthesizer This section documents the routing guidelines for the Hub Interface 1.5 that is responsible for connecting the MCH to the ICH3-S.
Page 90: Hub Interface 1.5 Generation/Distribution Of Reference Voltages
Hub Interface Table 7-6. Hub Interface 1.5 Signal Groups Signals Group ® Intel ICH3-S Common Clock Signals HI_A[11:8] HI[11:8] Source Synchronous Signals HI_A[7:0], HI_STBF, HI_STBS HI[7:0], HI_STBF, HI_STBS Miscellaneous Signals HIRCOMP_A, HISWNG_A, HIVREF_A HICOMP, HITERM, HIREF Table 7-7. Hub Interface 1.5 Routing Parameters...
Page 91: Hub Interface 1.5 Resistive Compensation
1.2V 1.8V 0.7 V 0.8 V HISWNG_A HITERM ® Intel ICH3-S HIVREF_A HIREF 0.35V 0.35 V The values of R1, R2, R3, R4 and R5 must be rated at ± 1% tolerance. The selected resistor values must also ensure that the reference voltage and reference swing voltage tolerance are maintained over the input leakage specification.
Page 92: Hub Interface 1.5 Decoupling Guidelines
Hub Interface 7.3.4 Hub Interface 1.5 Decoupling Guidelines To improve I/O power delivery, use two 0.1 µF capacitors per each component (i.e., the ICH3-S and MCH). These capacitors should be placed within 150 mils of each package, adjacent to the rows that contain the hub interface.
Page 93: 82870P2 (P64H2)
133 MHz 3.3 V NOTE: Frequencies specified are not the only ones supported, rather the maximum allowed in the configuration. Intel simulated the PCI/PCI-X bus topologies shown in Section 8.1.1 Section 8.1.2. If a platform implements a PCI/PCI-X topology not found in the following sections, it is the responsibility of the system designer to ensure the system meets the specified timings.
Page 94: Pci/Pci-X Routing Requirements (No Hot Plug)
8-1. Multiple slots are connected in a daisy chain topology with the device(s) down on the motherboard at the end of the daisy chain. Table 8-2 documents the lengths for the configurations Intel simulated. Figure 8-1. Typical PCI/PCI-X Routing Slot 1 ®...
Page 95: Pci/Pci-X Hot Plug Routing Requirements
8-2. Hot Plug switches are connected in a daisy chain topology with the device(s) down on the motherboard at the end of the daisy chain. Table 8-3 documents the lengths for the configurations that Intel simulated. Figure 8-2. Typical Hot Plug Routing Slot 1 P64H2 to...
Page 96: Clock Configuration
® Intel 82870P2 (P64H2) 8.1.3 Clock Configuration All PCI clocks must be disabled in the BIOS for any unused/unpopulated PCI/PCI-X slots. The PxPCLKO[5:0] pins can each be disabled by writing to the Disable PCLKOUT 5 – 0 bits (DPCLK, bits 15:10, config register offset 40h in each bridge). These clocks function the same in Serial and 2-Slot Parallel modes.
Page 97: Loop Clock Configuration
® Intel 82870P2 (P64H2) 8.1.4 Loop Clock Configuration You must tie PxPCLKO[6] to PxPCLKI because this clock always runs and is needed by the internal PCI PLLs to properly align output signals with the external clocks by removing clock insertion delay. The PxPCLKO[6] signal does not have to be routed through a bus switch before returning to PxPCLKI.
Page 98: Idsel Implementation
The SMBus interface does not have configuration registers. The SMBus address is set by the states of pins PA_GNT[5:4] and PB_GNT[5:4] when PWROK is asserted as described in Table 8-7. ® Refer to the Intel PCI-64 Hub 2 (P64H2) Datasheet for a more detailed description of P64H2 strap latching. Table 8-7. SMBus Address Configuration Value...
Page 99: Hot Plug Implementation
® Intel 82870P2 (P64H2) Hot Plug Implementation The P64H2 contains two integrated Hot Plug Controllers (one per PCI/PCI-X interface) that operate independently. These integrated controllers can be individually disabled or configured to operate in one of the three defined modes of operation: Single Slot Parallel mode, Dual Slot Parallel mode, and Serial mode.
Page 100: Hot-Insertions
® Intel 82870P2 (P64H2) 8.2.1.2 Hot-Insertions 1. User selects an empty, disabled slot and opens MRL. 2. User inserts add-in card, closes MRL, and attaches cables to card. 3. User requests that slot be enabled. a. User requests that slot be enabled via a software user interface.
Page 101: Manually-Operated Retention Latch Sensor
® Intel 82870P2 (P64H2) 8.2.2.1 Manually-Operated Retention Latch Sensor The HxSWITCH signal is monitored by the Hot Plug Controller to determine whether or not a slot should be powered. The MRL sensor, or slot switch, should be connected to the HxSWITCH pin such that it drives this pin low to indicate that the slot is closed and can be powered on.
Page 102: Optional Attention Button
® Intel 82870P2 (P64H2) 8.2.2.2 Optional Attention Button The Attention Button state is observed on the slot-specific HxPRSNT1# pin. An exclusive-OR (XOR) gate is inserted between the Slot Present signal and the Hot Plug Controller as shown in Figure 8-8. A momentary contact button is connected to the other input of the XOR gate. When the button is in the released state, the Slot Present signal is unaffected.
Page 103: Disabling/Enabling An Intel ® P64H2 Hot Plug Controller
® Intel 82870P2 (P64H2) ® 8.2.4 Disabling/Enabling an Intel P64H2 Hot Plug Controller 8.2.4.1 Hot Plug Strapping Options The HPxSLOT [2:0] strapping pins are used to enable and disable the Hot Plug Controller. Table 8-8 lists the strapping options associated with these pins, and the modes of operation they enable.
Page 104: Debounced Hot Plug Switch Input
® Intel 82870P2 (P64H2) 8.2.5.3 Debounced Hot Plug Switch Input The switch inputs (Px_IRQ[15] in this case—see Table 8-10) to the Hot Plug controller do not require any debouncing logic in this mode. This logic is contained within the P64H2. The POWERON value for this input is determined by BIOS.
Page 105: Hot Plug Muxed Signals In Single Slot Parallel Mode
® Intel 82870P2 (P64H2) Figure 8-10. MUX Circuit Example This signal could be pulled up to VCC_3.3 1 k Ω 2:1 Multiplexer depending on the strapping need. (PCIXCAP1 / PCIXCAP2) or HPxSLOT Strap VCC_3.3 PCIXCAP1 / PCIXCAP2 Truth Table C (PWROK) 8.2 kΩ...
Page 106: Smbus Address Considerations
® Intel 82870P2 (P64H2) Table 8-11. Hot Plug Controller Output Signal Reset Values Signals Reset Value Px_GNT[5:3] HPx_SOC HPx_SIC HPx_SOL HPx_SOLR HPx_SOD HPx_SORR# HPx_SOR# HPx_SIL# 8.2.5.7 SMBus Address Considerations In Single Slot Parallel mode, the SMBus address strap pins listed in...
Page 107: Reference Schematic For Single-Slot Parallel Mode
® Intel 82870P2 (P64H2) 8.2.5.9 Reference Schematic for Single-Slot Parallel Mode Note that the following schematics are based on definition and simulation of the P64H2. These schematics have not been fully validated. Figure 8-12. Reference Schematic for Single-Slot Parallel Mode...
Page 108: Dual Slot Parallel Mode
® Intel 82870P2 (P64H2) 8.2.6 Dual Slot Parallel Mode Dual Slot Parallel Mode is used when it is desirable to have two slots that are Hot Pluggable. No serialization/deserialization logic is required for this mode of operation. 8.2.6.1 Required Additional Logic Dual Slot Parallel Mode requires a power switch to be used to turn the slot power on and off.
Page 109: Hot Plug Muxed Signals In Dual Slot Parallel Mode
8.2.6.7 Hot Plug Muxed Signals in Dual Slot Parallel Mode The Hot Plug signals that connect to the controller are as follows: Table 8-12. Dual Slot Parallel Mode Hot Plug Signals Table ® Muxed Intel P64H2 Pin Note Signal Type...
Page 110: Smbus Address Considerations
® Intel 82870P2 (P64H2) 8.2.6.8 SMBus Address Considerations In Dual Slot Parallel mode, the SMBus address strap pins in Table 8-7 are muxed as Hot Plug control signals HxRESETA# and HxBUSENB#. Therefore, it is recommended that the following technique be used for determining an SMBus address. Pull the PA_GNT5 (RESETA#) signals to ground through a 100 ±...
Page 111: Reference Schematic For Dual-Slot Parallel Mode
® Intel 82870P2 (P64H2) 8.2.6.9 Reference Schematic for Dual-Slot Parallel Mode Note that the following schematics are based on definition and simulation of the P64H2. These schematics have not been fully validated. Figure 8-14. Reference Schematic for Dual-Slot Parallel Mode PxPCLK O [0] Note * All PCI signals m uxed or not need to follow PCI spec 2.2 pullup requirem ents...
Page 112: Three Or More Slot Serial Mode
® Intel 82870P2 (P64H2) 8.2.7 Three or More Slot Serial Mode Serial Mode allows for three to six slots to be hot pluggable. This mode can also be used to enable slots that are hot pluggable, and others that are not on the same PCI/PCI-X bus.
Page 113: Pull-Ups/Pull-Downs In Three Or More Slot Serial Mode
® Intel 82870P2 (P64H2) Table 8-13. Shift Register Input Data Byte 0 Byte 1 Byte 2 Byte 3 Slot 1 switch (0 = closed) Slot 1 fault# (0 = fault) Slot 1 present bit 2 Slot 1 present bit 1...
Page 114: Reference Schematic For Serial Mode
Pwren [2:4] to power routed to each PCI Slot enable logic for PCI slots by means of a bus 3.3V [2:4] ® switch so that the Intel Depending on the GPOA [7:0] 3.3V Green LED 1 serialization/ 828702P2 can drive this...
Page 115: Intel ® P64H2 Pci Interface Pcixcap And M66En Pins
® Intel 82870P2 (P64H2) ® 8.2.8 Intel P64H2 PCI Interface PCIXCAP and M66EN Pins 8.2.8.1 PCIXCAP Pin Requirements During all modes of the P64H2 Hot Plug Controller operation, the P64H2 PCI/PCI-X interface pin PxPCIXCAP is not used. This pin should be tied to either 3.3 VCC or ground through an 8.2 kΩ...
Page 116: M66En Isolation Switch Solution
® Intel 82870P2 (P64H2) M66EN Isolation Switch Solution One possible solution is to place a single 5 ± 5% pull-up on the P64H2 side of the isolation kΩ logic and a 5 ± 5% pull-up on the slot side after the isolation logic, but with its own isolation kΩ...
Page 117: M66En Diode Solution
® Intel 82870P2 (P64H2) M66EN Diode Solution Another possible solution is to use diodes to isolate the individual slots from one another while still allowing the P64H2 to drive the M66EN signals to ground. The P64H2 PCI interface PxM66EN signal should be pulled to 3.3 V through a 100 ±...
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Page 119: I/O Controller Hub
I/O Controller Hub I/O Controller Hub IDE Interface This section contains guidelines for connecting and routing the ICH3-S IDE interface. The ICH3-S has two independent IDE channels. This section provides guidelines for IDE connector cabling and motherboard design, including component and resistor placement, and signal termination for both IDE channels.
Page 120: Cable Detection For Ultra Ata/66 And Ultra Ata/100
IDE device. If a 40-conductor cable is detected, the system software must not enable modes faster than Ultra DMA Mode 2 (Ultra ATA/33). Intel recommends that cable detection be performed using a combination Host-Side/Device-Side detection mechanism. 9.1.2.1 Combination Host-Side/Device-Side Cable Detection Host side detection (described in the ATA/ATAPI-4 Standard, Section 5.2.11) requires the use of...
Page 121: Primary Ide Connector Requirements
Figure 9-2. Connection Requirements for Primary IDE Connector 22–47 Ω PCIRST# IDERST# PDD[15:0] PDA[2:0] PDCS[3,1]# PDIOR# PDIOW# PDDREQ PDDACK# ® Intel ICH3-S 3.3 V 3.3 V 4.7 kΩ 8.2–10 kΩ PIORDY (PRDSTB/PWDMARDY#) IRQ14 PDIAG# / CBLID# GPIOx 10 kΩ CSEL NOTE: Because of ringing, PCIRST# must be buffered.
Page 122: Secondary Ide Connector Requirements
Figure 9-3. Connection Requirements for Secondary IDE Connector 22–47 Ω PCIRST# IDERST# SDD[15:0] SDA[2:0] SDCS[3,1]# SDIOR# SDIOW# SDDREQ SDDACK# ® Intel ICH3-S 3.3 V 3.3 V 4.7 kΩ 8.2–10 kΩ SIORDY (SRDSTB/SWDMARDY#) IRQ15 SDIAG# / CBLID# GPIOx 10 kΩ CSEL NOTE: Because of ringing, PCIRST# must be buffered.
Page 123: Spkr Pin Consideration
(0.5 VCC_3.3 to VCC_3.3 + 0.5 V). Figure 9-4. Example Speaker Circuit VC C3_3 Stuff jumper to disable R value is timeout feature (no reboot). implementation specific. ® Intel ICH3-S SPKR Effective impedance due to speaker. Integrated Ω Ω 13 k...
Page 124: Usb
I/O Controller Hub Figure 9-5. PCI Bus Layout Example ® Intel ICH3-S The ICH3-S contains three UHCI Host Controllers. Each UHCI Controller includes a root hub with two separate USB ports, for a total of six USB ports. This section provides guidelines for routing USB.
Page 125: Usb Trace Separation
I/O Controller Hub 9. Keep traces at least 50 mils away from the edge of the plane. This helps prevent the coupling of the signal onto adjacent wires, and helps prevent free radiation of the signal from the edge of the PCB. 9.4.2 USB Trace Separation Use the following separation guidelines.
Page 126: Usb Power Line Layout Topologies
LAN Controller will claim the SMLink heartbeat and event messages and send them out over the ® network. An external, Alert on LAN2-enabled LAN Controller (i.e., Intel 82550) will connect to the SMLink signals to receive heartbeat and event messages, as well as access the ICH3-S SMBus Slave Interface.
Page 127: Smbus Design Considerations
Controller Intel does not support external access of the ICH3-S's Integrated LAN Controller via the SMLink interface. In addition, Intel does not support access of the ICH3-S's SMBus Slave Interface by the ® ICH3-S's SMBus Host Controller. Refer to the Intel 82801CA I/O Controller Hub 3 (ICH3-S) Datasheet for full functionality descriptions of the SMLink and SMBus interface.
Page 128: Real Time Clock (Rtc)
Full-Swing 32.768kHz SUSCLK Output Signal ® For further information on the RTC, consult Intel application note AP-728 Intel ICH Family Real Time Clock (RTC) Accuracy and Considerations Under Test Conditions (http:// developer.intel.com/design/chipsets/applnots/292276.htm). This section presents the recommended hookup for the RTC circuit for the ICH3-S.
Page 129: Rtc External Circuit
I/O Controller Hub 9.6.1 RTC External Circuit The ICH3-S RTC module requires an external oscillating source of 32.768 kHz connected on the RTCX1 and RTCX2 balls. Figure 9-10 documents the external circuitry that comprises the oscillator of the ICH3-S RTC. Figure 9-10.
Page 130: External Capacitors
Cin1, Cin2 = input capacitances at RTCX1, RTCX2 balls of the ICH3-S. These values can be ® obtained in the Intel 82801CA I/O Controller Hub 3 (ICH3-S) Datasheet. Ctrace1, Ctrace2 = Trace length capacitances measured from crystal terminals to the RTCX1 and RTCX2 balls.
Page 131: Rtc Layout Considerations
I/O Controller Hub 9.6.3 RTC Layout Considerations Since the RTC circuit is very sensitive and requires high accurate oscillation, reasonable care must be taken during layout and routing of the RTC circuit. Some recommendations are: • Reduce trace capacitance by minimizing the RTC trace length. ICH3-S requires a trace length less than 1 inch on each branch (from crystal's terminal to RTCXn ball).
Page 132: Rtc External Rtcrst# Circuit
RTC oscillation. Probing VBIAS requires the same technique as probing the RTCX1 and RTCX2 signals (using ® Op-Amp). See application note AP-728, Intel ICH Family Real Time Clock (RTC) Accuracy and Considerations Under Test Conditions, for further details on measuring techniques.
Page 133: Susclk
I/O Controller Hub 9.6.7 SUSCLK SUSCLK is a square waveform signal output from the RTC oscillation circuit. Depending on the quality of the oscillation signal on RTCX1 (largest voltage swing), SUSCLK duty cycle can be between 30% and 70%. If the SUSCLK duty cycle is beyond the 30%–70% range, there is a poor oscillation signal on RTCX1 and RTCX2.
Page 134: Platform Lan Connect
Table 9-1. LAN Design Guide Section Reference Figure 9-14 Layout Section Design Guide Section Reference ® Section 9.7.1, Intel ICH3-S – LCI (LAN Connect ICH3-S – LAN Connect Interface Interface) Guidelines Section 9.7.2, General LAN Routing Guidelines General Routing Guidelines and Consideration ®...
Page 135: Lci (Lan Connect Interface) Guidelines
The LAN Connect Interface must be configured in direct point-to-point connection between the ICH3-S and the LAN component topology. (Refer to Figure 9-15.) Figure 9-15. Point-to-Point Interconnect Guideline L = 4.5" – 10" ® LAN_CLK Intel LAN_RSTSYNC 82562ET ® Intel ICH3-S LAN_RXD[2:0] ®...
Page 136: Signal Routing And Layout
I/O Controller Hub 9.7.1.2 Signal Routing and Layout Route the LCI signals carefully on the motherboard to meet the timing and signal quality requirements of this interface specification. The board designer should simulate the board routing to verify that the specifications are met for flight times and skews due to trace mismatch and crosstalk.
Page 137: General Lan Routing Guidelines And Considerations
I/O Controller Hub 9.7.2 General LAN Routing Guidelines and Considerations 9.7.2.1 General Trace Routing Considerations Trace routing considerations are important to minimize the effects of crosstalk and propagation delays on sections of the board where high-speed signals exist. Signal traces should be kept as short as possible to decrease interference from other signals, including those propagated through power and ground planes.
Page 138: Trace Geometry And Length
I/O Controller Hub 9.7.2.2 Trace Geometry and Length The key factors in controlling trace EMI radiation are the trace length, and the ratio of trace-width to trace-height above the ground plane. To minimize trace inductance, high-speed signals and signal layers that are close to a ground or power plane should be as short and wide as practical. Ideally, this trace width to height above the ground plane ratio is between 1:1 and 3:1.
Page 139: General Power And Ground Plane Consideration
I/O Controller Hub 9.7.2.5 General Power and Ground Plane Consideration To properly implement the common mode choke functionality of the magnetics module, the chassis or output ground (secondary side of transformer) should be separated from the digital or input ground (primary side) by a physical separation of 100 mils minimum. Figure 9-18.
Page 140: Board Design
I/O Controller Hub 9.7.2.6 Board Design The following recommendations are based on a ground referenced design. • Top Layer Routing Sensitive analog signals are routed completely on the top layer without the use of vias. This allows tight control of signal integrity, and removes any impedance inconsistencies due to layer changes.
Page 141 I/O Controller Hub • Use of an inferior magnetics module. The magnetics modules that we use have been fully tested for IEEE PLC conformance, long cable BER, and for emissions and immunity. (Inferior magnetics modules often have less common-mode rejection and/or no auto transformer in the transmit channel.) •...
Page 142: Intel ® 82562Et/Em Guidelines
82562ET or 82562EM Platform LAN connect component are provided in the following sections. ® 9.7.3.1 Guidelines for Intel 82562ET/EM Component Placement Component placement can affect signal quality, emissions, and temperature of a board design. This section provides guidelines for component placement.
Page 143: Intel ® 82562Et/Em Termination Resistors
Platform LAN connect component (82562ET or 82562EM) as possible. This is due to the fact that these resistors are terminating the entire impedance that is seen at the termination source (i.e., 82562ET), including the wire impedance reflected through the transformer. ® Figure 9-19. Intel 82562ET/EM Termination LAN Connect Interface ®...
Page 144 I/O Controller Hub Distance from Magnetics Module to RJ45 (Distance A) The distance A in Figure 9-20 should be given the highest priority in board layout. The distance between the magnetics module and the RJ45 connector should be kept to less than one inch of separation.
Page 145: Terminating Unused Connections
I/O Controller Hub 9.7.5 Terminating Unused Connections In Ethernet designs, it is common practice to terminate unused connections on the RJ45 connector and the magnetics module to ground. Depending on overall shielding and grounding design, this may be done to the chassis ground, signal ground, or a termination plane. Care must be taken when using various grounding methods to insure that emission requirements are met.
Page 146 I/O Controller Hub This page is intentionally left blank. Design Guide...
Page 147: Debug Port
10.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging the system bus of Intel Xeon processors. Contact Tektronix, Inc. and Agilent Technologies to get specific information about their logic analyzer interfaces. The following information is general in nature.
Page 148 Debug Port This page is intentionally left blank. Design Guide...
Page 149: Emi And Mechanical Design Considerations
EMI and Mechanical Design Considerations EMI and Mechanical Design Considerations 11.1 Introduction As microprocessor amperage and speeds increase, the ability to contain the corresponding electromagnetic radiation becomes more difficult. Frequencies generated by these processors will be in the low gigahertz (GHz) range, which will impact both the system design and the electromagnetic interference (EMI) test methodology.
Page 150: Emi Regulations And Certifications
EMI Design Considerations The following sections describe design techniques that may be applied to minimize EMI emissions. Some techniques have been incorporated into Intel-enabled designs (differential clock drivers, selective clock gating, etc.), and some must be implemented by motherboard designers (trace routing, clocking schemes, etc.).
Page 151: Differential Clocking
EMI and Mechanical Design Considerations Figure 11-1. Spread Spectrum Modulation Profile time δ Figure 11-2. Impact of Spread Spectrum Clocking on Radiated Emissions ∆ non-SSC (1-δ)f 11.2.2 Differential Clocking Differential clocking requires that the clock generator supply both clock and clock-bar traces. Clock-bar has equal and opposite current as the primary clock, and is also 180 degrees out of phase.
Page 152: Pci Bus Clock Control
EMI and Mechanical Design Considerations Figure 11-3. Cancellation of H-fields Through Inverse Currents H-field CLK - clock trace caused by Iclk CLK' - clock bar Iclk trace Iclk' H-field caused by Iclk' Differential clocking can also reduce the amount of noise coupled to other traces, which improves signal quality and reduces EMI.
Page 153: Heatsink Effects
Faraday cage can be achieved. Intel has designed a “picture frame” type of grounding device, called an EMI ground frame, that fits between the processor and heatsink (see Figure 11-4).
Page 154: Emi Test Capabilities
EMI and Mechanical Design Considerations Figure 11-4. Conceptual Processor Ground Frame 11.2.6 EMI Test Capabilities FCC regulations in the United States specify the maximum test frequency for products with clocks in excess of 1 GHz is five times the highest clock frequency or 40 GHz, which ever is lower. OEMs are advised to inquire into the capabilities of their preferred EMC test lab to ensure they are able to scan up to the required frequency range.
Page 155: Retention Mechanism Placement And Keep-Outs
11.3 Retention Mechanism Placement and Keep-Outs The retention mechanism (RM) for the Intel Xeon processor requires two keep-out zones: one for the EMI ground pads, and another for a limited component height area under the RM as shown in Figure 11-5.
Page 156: Retention Mechanism Placement And Keep-Out Overview
EMI and Mechanical Design Considerations Figure 11-6. Retention Mechanism Placement and Keep-Out Overview Socket PIN #1 Location Socket Shown For Reference O nly Maximum Component Height 1.150 " 0.35 " Unless Otherwise Specified . .000 " 1. 500 " .002 ∅...
Page 157: Grounding Techniques
The grounding frame for the Intel Xeon processor is meant to provide grounding of AC currents seen on the heatsink, and has been shown to be the most effective design in EMI reduction for the processor.
Page 158: Retention Mechanism Ground Ring
EMI and Mechanical Design Considerations Utilization of the DC grounding strips requires ground pads around the mounting holes for the retention mechanism. Metal inserts will be pre-assembled to the retention modules to establish DC contact between heatsink base plate and the motherboard ground. The inserts will be grounded to the baseboard at mounting hole ground pads.
Page 159: Platform Power Delivery Guidelines
Platform Power Delivery Guidelines Platform Power Delivery Guidelines This chapter depicts an example for board power delivery and the power requirements for some board components. 12.1 Customer Reference Board Power Delivery Figure 12-1 shows the power delivery architecture for the E7500 Chipset Customer Reference Board.
Page 160: Power Delivery Example
IccSus_3.3(max) = 14.01 mA (HI I/O & Core) 14.01 mA 1.8 V Icore(max) = 2.66 A VccSus_1.8 (Resume Logic) 1.8 V ® Intel Vcc3.3 IccSus_1.8(max) = 64 mA P64H2 (PCI.X I/O) VcpuIO 3.3 V (CPU CMOS I/O) Ivcc3.3(max) = 1.3 A VccP (def.
Page 161: Processor Core Voltage
1.30 V and 1.50 V. A VRM 9.1 compatible design is required for all Xeon platforms. The Voltage Regulator solution can be either a VRM 9.1 or a VRDown design. Refer to the Voltage Regulator Module (VRM) 9.1 DC-DC Converter Design Guidelines, Dual ®...
Page 162: Vsb
Processor Power Distribution Guidelines 12.2.1 Processor Power Requirements This section describes the requirements for supplying power to a Intel Xeon processor. For detailed ® electrical specifications, refer to the Intel Xeon™ Processor with 512 KB L2 Cache at 1.80 GHz, 2 GHz, and 2.20 GHz Datasheet.
Page 163: Voltage Tolerance
® Refer to the Intel Xeon™ Processor with 512 KB L2 Cache at 1.80 GHz, 2 GHz, and 2.20 GHz Datasheet for voltage tolerance specifications. Failure to meet these specifications on the low-end tolerance results in transistors slowing down and not meeting timing specifications. Not meeting the specifications on the high-end tolerance can cause damage or reduce the life of the processor.
Page 164: Voltage Regulator Requirements
(the east and west side). The Intel Xeon processor socket has 603 pins with 50 mil pitch. The routing of the signals, power, and ground pins require creation of lots of vias. These vias cause a “Swiss cheese” effect in the power and ground planes beneath the processor, resulting in increased inductance of these planes.
Page 165: Input Voltages And Currents
The VID values are documented in ® the Intel Xeon™ Processor with 512 KB L2 Cache at 1.80 GHz, 2 GHz, and 2.20 GHz Datasheet. 12.2.4.1 Input Voltages and Currents To minimize power distribution losses, the recommended main power source for the VR is 12 V +5%, 8%.
Page 166: Fault Protection
Ishare. This pin will be connected to other VRM 9.1s within the system. The VRM 9.1 output slew rate is specified at 50 A/µs. The slew rate for the Intel Xeon processor is 450A/µs at the socket pins. The system designer must provide adequate bulk and high-frequency decoupling on the motherboard to meet the appropriate processor required slew rate.
Page 167: Vr Down Recommendations
Platform Power Delivery Guidelines Figure 12-3. VRM VID Routing Voltage Regulator Processor 0 Module 1 Power Supply Voltage Regulator Processor 1 Module 2 OUTEN VIDx[4:0] Output Enable Logic 12.2.6 VR Down Recommendations Figure 12-4 is a simplified block diagram of a four-phase, interleaved VRD implementation. Figure 12-4.
Page 168: Example Load Line Selection Circuit
Platform Power Delivery Guidelines Single or Dual Processor Operation Many OEMs require that a dual-processor VRD supplying an Intel processor’s common voltage plane operate with either one or two processors installed on the board (i.e., the design must meet the static and transient voltage characteristics of both the dual- and single-processor load lines). A solution is to adjust the load line for the number of installed processors.
Page 169: Voltage Sequencing
VCC_CPU and SM_VCC. SM_VCC is required for correct operation of the Intel Xeon processor VID logic.The Intel Xeon processor’s VID outputs use an active driver. A 3.3 V source connected to the processor’s SM_VCC pins supplies the VID output devices.
Page 170: Power-Up And Power-Down Timing
Platform Power Delivery Guidelines Figure 12-7. Power-Up and Power-Down Timing Power Up =95% 3.3 volt level 3.3 VDC/SM_VCC PW R_OK / OUTEN > T + 100ms VID_OUT + 10m S PW RGD Processor PW RGOOD Processor RESET 1ms<T<10ms Power Dow n 95% 3.3 volt level 3.3 VDC/SM_VCC PW ROK...
Page 171: Vcca, Vcciopll, And Vssa Filter Specifications
Platform Power Delivery Guidelines 12.2.8 VCCA, VCCIOPLL, and VSSA Filter Specifications VCCA and VCCIOPLL are required by the processor’s internal PLL. These voltages are created by using a low pass filter on VCC_CPU. The processor has internal analog PLL clock generators that require quiet power supplies for minimum jitter.
Page 172: Filter Implementation 1: Using Discrete Resistor
Platform Power Delivery Guidelines To satisfy damping requirements, total series resistance in the filter (from VCC_CPU to the top plate of the capacitor) must be at least 0.35 Ω. This includes the DCR of the inductor and any resistance (routing or discrete components) between VCC_CPU and capacitor top plate. Keep the routing short and wide.
Page 173: Processor Decoupling
A load-change transient occurs when coming out of or entering a low power mode. Load-change transients for the Intel Xeon processor are on the order of 55 A. These are not only quick changes in current demand, but also long lasting average current requirements. This occurs when the STPCLK# pin is asserted or de-asserted, and during Auto HALT.
Page 174: Decoupling Example For A Microstrip Baseboard Design
Platform Power Delivery Guidelines In addition, high-frequency decoupling may be required for signal integrity. System boards designed using striplines with VCC_CPU and VSS references should not require high-frequency decoupling beyond the recommendations listed in Table 12-5. For systems using microstrip configurations, a return path discontinuity will exist between the processor and the baseboard due to the baseboard traces having only one reference plane.
Page 175: Bulk Decoupling
Platform Power Delivery Guidelines 12.2.9.2 Bulk Decoupling Table 12-6 lists the recommended bulk capacitance parameters for Intel Xeon processors. The following recommendations indicate the decoupling suggested for each processor in the system. Table 12-6. Processor Bulk Capacitance Recommendations RMS Current...
Page 176: Suggested Gtlref Generation
Platform Power Delivery Guidelines Use two voltage dividers for each processor, and one for the chipset component. Assume a maximum of 15 mA of leakage current per load. These leakage currents can be positive or negative. The following discussion illustrates using a single voltage divider to support two GTLREF Loads assuming VCC_CPU of 1.475 V.
Page 177: Component Models
12.2.12 Measuring Transients Intel recommends the following guidelines when measuring the transients on VCC_CPU. The measurement should be performed across the VCC_CPU and VSS pins on the processor socket. Use an oscilloscope with 500 MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 MΩ...
Page 178: Ddr (2.5 V Power Plane)
Platform Power Delivery Guidelines 12.3.3 DDR (2.5 V Power Plane) A maximum of seven 0.1µF (minimum of five) capacitors are recommended (with 900 pH to 1.1 nH inductance) to be placed under the MCH for DDR 2.5 V power plane decoupling (see Figure 12-15).
Page 179: Filter Specifications (1.2V Power Plane)
Platform Power Delivery Guidelines 12.3.5 Filter Specifications (1.2V Power Plane) VCCA_1.2 and VCCAHI_1.2 are created by using a low pass filter on VCC_1.2. VCCACPU is created by using a low pass filter on VCC_CPU. The MCH has internal analog PLL clock generators, which require quiet power supplies for minimum jitter.
Page 180: Mch Power Sequencing Requirement
Platform Power Delivery Guidelines Figure 12-18. Filter Topology for VCCAHI_1.2 (System Bus) Within 1" RLC Network VCC_CPU of Ball Within 1" 1 Ω 100 nH VCCACPU 100 µF 0.1 µF Route to ball U15 12.3.6 MCH Power Sequencing Requirement The MCH has only one power sequencing requirement. The MCH requires that 1.2 V rises with or before 2.5 V to avoid electrical overstress of oxide layers and possible component damage.
Page 181: Intel ® Ich3-S Power Delivery Guidelines
VCC_1.2 0.1 µF – ® 12.4 Intel ICH3-S Power Delivery Guidelines 12.4.1 1.8 V/3.3 V Power Sequencing The ICH3-S has two pairs of associated 1.8 V and 3.3 V supplies. These are {VCC_1.8, VCC_3.3} and {VCCSUS_1.8, VCCSUS_3.3}. The difference between the two associated supplies must never be greater than 2.0 V.
Page 182: V/V5Ref Sequencing
Platform Power Delivery Guidelines Figure 12-21. Example 1.8 V/3.3 V Power Sequencing Circuit +3.3V +1.8V 220 Ω 220 Ω 470 Ω When analyzing systems that may be “marginally compliant” to the 2 V Rule, attention must be paid to the behavior of the ICH3-S’s RSMRST# and PWROK signals because they control internal isolation logic between the various power planes: •...
Page 183: Intel ® Ich3-S Power Rails
5 V Supply 1 kΩ 1 µF VREF To System To System ® 12.4.3 Intel ICH3-S Power Rails The ICH3-S refers to it’s standby rails as suspend. Table 12-8 lists the nomenclature. Table 12-8. ICH3-S Power Rail Terminology Platform Terminology ICH3-S Terminology...
Page 184: Intel ® Ich3-S Decoupling Recommendations
Platform Power Delivery Guidelines ® Table 12-9. Intel ICH3-S Decoupling Recommendations Power Decoupling Requirements Decoupling Placement • Locate within 100 mils of the V_CPU_IO Use one 0.1 µF decoupling capacitor. ICH3-S processor interface balls. • Locate within 100 mils of the Use one 1.0 µF decoupling capacitor.
Page 185: Intel® P64H2 Power Requirements
P64H2 Power Requirements ® 12.5.1 Intel P64H2 Current Requirements ® Table 12-10. Intel P64H2 Max Sustained Currents Voltage at PCI/PCI-X Interface Max Sustained Current 1.8V at 33 MHz PCI (both segments) 1970 mA 1.8V at 66 MHz PCI/PCI-X (both segments) 2170 mA 1.8V at 100 MHz PCI-X (both segments)
Page 186: Pcirst# Implementation
PCI-X requires a 100 ms delay from valid power (PWRGD) to reset deassertion (PCIRST#). The system design must ensure this requirement is met. The P64H2 reset must be deasserted within 60 ns of the MCH reset deassertion. Intel strongly recommends the customer to measure this timing relationship on their board. Failure to meet this guideline may result in a system failing to boot.
Page 187: Schematic Checklist
Schematic Checklist Schematic Checklist 13.1 Processor Schematic Checklist Table 13-1. Processor Schematic Checklist (Sheet 1 of 6) Checklist Items Recommendations Comments A20M# • Connect to both processors and ICH3-S. • Asynchronous GTL+ Input Signal. Include 200 Ω ± 5% pull-up to VCC_CPU. •...
Page 188 Schematic Checklist Table 13-1. Processor Schematic Checklist (Sheet 2 of 6) Checklist Items Recommendations Comments BPRI# • Connect to both processors and the MCH. • Used to arbitrate for ownership of the processor system bus. • AGTL+ Common Clock Input. •...
Page 189 Schematic Checklist Table 13-1. Processor Schematic Checklist (Sheet 3 of 6) Checklist Items Recommendations Comments DSTBN[3:0]# • Connect to both processors and the MCH. • Data strobe used to latch in D[63:0]# DSTBP[3:0]# • Maintain a 25 mil spacing from other signals.
Page 190 Schematic Checklist Table 13-1. Processor Schematic Checklist (Sheet 4 of 6) Checklist Items Recommendations Comments ODTEN • Enable on-die termination (ODT) on • Enables processor on-die Processor 0 (end processor) by pulling up to termination. VCC_CPU with a 50 Ω ± 20% resistor. •...
Page 191 SMBus address for the memory devices on • These signals have 10 k Ω pull- ® the processor. See the Intel Xeon™ downs on the processor . Processor with 512 KB L2 Cache at 1.80 GHz, 2 GHz, and 2.20 GHz Datasheet for •...
Page 192 Schematic Checklist Table 13-1. Processor Schematic Checklist (Sheet 6 of 6) Checklist Items Recommendations Comments • Option 1: Recommend separate 50 Ω ± 20% TESTHI[6:0] • Input. pull-up to VCC_CPU. • Refer to Section 5.3.8. • Option 2: TESTHI[3:0] and TESTHI[6:5] may all be tied together and pulled up to VCC_CPU with a single 50 Ω...
Page 193: Mch Schematic Checklist
Schematic Checklist 13.2 MCH Schematic Checklist Table 13-2. MCH Schematic Checklist (Sheet 1 of 3) Checklist Items Recommendations Comments Host Interface ADS# • See processor section of this checklist. AP[1:0] BINIT# BNR# BPRI# BREQ0# CPURST# DBI[3:0]# DBSY# DEFER# DP[3:0]# DRDY# HA[35:3]# HD[63:0]# HADSTB[1:0]#...
Page 194 Schematic Checklist Table 13-2. MCH Schematic Checklist (Sheet 2 of 3) Checklist Items Recommendations Comments Hub Interface A HI[11:0] • Maximum length of 20" (stripline routing). • Refer to Section 7.3.1. HI_STBF • Connect to ICH3-S. • Refer to Section 7.3.1.
Page 195 Schematic Checklist Table 13-2. MCH Schematic Checklist (Sheet 3 of 3) Checklist Items Recommendations Comments Unused 16 bit • All data and strobe signals can be left as no • The MCH has integration interfaces connect. detection logic that will detect unpopulated 16-bit interfaces •...
Page 196: Intel ® Ich3-S Schematic Checklist
Schematic Checklist ® 13.3 Intel ICH3-S Schematic Checklist Note: There are no inputs to the ICH3-S that can be left floating. ® Table 13-3. Intel ICH3-S Schematic Checklist (Sheet 1 of 8) Checklist Items Recommendations Comments Processor Signals A20M# • Refer to the signal recommendations under CPUSLP# (SLP#) the Processor Schematic Checklist.
Page 197 Schematic Checklist ® Table 13-3. Intel ICH3-S Schematic Checklist (Sheet 2 of 8) Checklist Items Recommendations Comments GPIO[43:32] • I/O pins. Defaults as an output when enabled as GPIOs. • From main power well (VCC_3.3). Hub Interface HI[11] • No pull-up resistor required.
Page 198 Schematic Checklist ® Table 13-3. Intel ICH3-S Schematic Checklist (Sheet 3 of 8) Checklist Items Recommendations Comments • The 10 k Ω resistor to GND Cable Detect • Host Side/Device Side Detection (recommended method): prevents GPI from floating if no devices are present on either –...
Page 199 Schematic Checklist ® Table 13-3. Intel ICH3-S Schematic Checklist (Sheet 4 of 8) Checklist Items Recommendations Comments LAN Interface LAN_CLK • Connect to LAN_CLK on Platform LAN • Refer to Section 9.7. Connect Device. LAN_RXD[2:0] • Connect to LAN_RXD on Platform LAN •...
Page 200 Schematic Checklist ® Table 13-3. Intel ICH3-S Schematic Checklist (Sheet 5 of 8) Checklist Items Recommendations Comments GNT[4:0]# • No external pull-up resistors are required on • These signals are actively PCI GNT signals. However, if external pull- driven by the ICH3-S.
Page 201 Schematic Checklist ® Table 13-3. Intel ICH3-S Schematic Checklist (Sheet 6 of 8) Checklist Items Recommendations Comments Power Management THRM# • Connect to temperature Sensor. Pull-up if • Input to ICH3-S cannot float. not used with an 8.2 k Ω ± 5% pull-up resistor THRM# polarity bit defaults to VCC_3.3.
Page 202 Schematic Checklist ® Table 13-3. Intel ICH3-S Schematic Checklist (Sheet 7 of 8) Checklist Items Recommendations Comments VBIAS • The VBIAS pin of the ICH3-S is connected • For noise immunity on VBIAS to a 0.047 µF capacitor. signal. • Refer to Figure 9-10.
Page 203 Schematic Checklist ® Table 13-3. Intel ICH3-S Schematic Checklist (Sheet 8 of 8) Checklist Items Recommendations Comments • Required 18.2 Ω ± 1% pull-down. USBRBIAS • Integrated 15 k Ω pull-down, USBP[5:0]P • No external resistors are required. USBP[5:0]N effective output driver impedance of 45 Ω...
Page 204: Intel ® 82870P2 P64H2 Schematic Checklist
Schematic Checklist ® 13.4 Intel 82870P2 P64H2 Schematic Checklist ® Table 13-4. Intel P64H2 Schematic Checklist (Sheet 1 of 5) Checklist Items Recommendations Comments Hub Interface BPCLK100 • These can be left as no connects. • These clock signals are used BPCLK133 for testing modes.
Page 205 Schematic Checklist ® Table 13-4. Intel P64H2 Schematic Checklist (Sheet 2 of 5) Checklist Items Recommendations Comments PCIXCAP • Conventional PCI cards connect this pin • See PCI-X Specification 1.0 directly to ground. recommendations for PCIXCAP PCI-X 133 cards connect PCIXCAP to ground connection.
Page 206 Schematic Checklist ® Table 13-4. Intel P64H2 Schematic Checklist (Sheet 3 of 5) Checklist Items Recommendations Comments PA_133EN • Enable PCI-X at 133 MHz for PCI Bus A. This • Only active if PA_PCIXCAP and PB_133EN pin, when high, allows the PCI-X segment to...
Page 207 Schematic Checklist ® Table 13-4. Intel P64H2 Schematic Checklist (Sheet 4 of 5) Checklist Items Recommendations Comments Hot Plug – Single Slot Parallel Mode Specific • Pulled to 3.3 Vcc through an 8.2 k Ω ± 5% PxIRQ[14:8] • These signals are mapped to resistor.
Page 208 PCIRST# active output from each PCI interface. • 8.2 k Ω ± 5% pull-up resistor to VCC3.3. TEST# • Intel Test Mode. • 8.2 k Ω ± 5% pull-up resistor to VCC3.3. RASERR# NOTE: 1. x = A or B...
Page 209: Ck408 Schematic Checklist
Schematic Checklist 13.5 CK408 Schematic Checklist Table 13-5. CK408 Schematic Checklist Checklist Items Recommendations Reason/Impact 66BUFF[2:0] • Connect to a P64H2 using a series • Refer to Section 4.1.2. 43 Ω ± 5% resistor. 66IN • No Connect. 3V66_0 • Connect to ICH3-S using a series •...
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Page 211: Layout Checklist
Layout Checklist Layout Checklist 14.1 Processor Checklist Table 14-1. Processor Layout Checklist (Sheet 1 of 2) Checklist Items Recommendations Comments A20M# • Connect to both processors and ICH3-S. • Asynchronous GTL+ Input IGNNE# Signals. • Trace impedance = 50 Ω ± 10%. INIT# •...
Page 212 Layout Checklist Table 14-1. Processor Layout Checklist (Sheet 2 of 2) Checklist Items Recommendations Comments COMP[1:0] • There are no routing requirements for these • Enables processor on-die ODTEN signals. termination. SKTOCC# • Input. TESTHI[6:0] • Refer to Section 5.3. VID[4:0] Reserved •...
Page 213: Intel® E7500 Mch Layout Checklist
Layout Checklist ® 14.2 Intel E7500 MCH Layout Checklist Table 14-2. MCH Layout Checklist (Sheet 1 of 3) Checklist Items Recommendations Comments Host Interface ADS# • See processor section of this checklist. AP[1:0] BINIT# BNR# BPRI# BREQ0# CPURST# DBSY# DEFER#...
Page 214 Layout Checklist Table 14-2. MCH Layout Checklist (Sheet 2 of 3) Checklist Items Recommendations Comments DQ[63:0] • Route entirely on the same layer from • Refer to Section 6.2. CB[7:0] MCH to DIMM to termination (no layer transitions). Place the 10 Ω series resistor DQS[17:0] <...
Page 215 Layout Checklist Table 14-2. MCH Layout Checklist (Sheet 3 of 3) Checklist Items Recommendations Comments Clocks, Reset, Miscellaneous Signals HCLKINP • HCLKs should be length matched to all • Refer to Section 4.1.1. HLCKINN processors BCLKs. See Table 4-3 routing guidelines. CLK66 •...
Page 216: Intel® Ich3-S Layout Checklist
Layout Checklist ® 14.3 Intel ICH3-S Layout Checklist ® Table 14-3. Intel ICH3-S Layout Checklist (Sheet 1 of 4) Checklist Items Recommendations Comments Processor Signals A20M# • See processor section of this checklist. CPUSLP# FERR# IGNNE# INIT# LINT[1:0] SMI# STPCLK#...
Page 217 Layout Checklist ® Table 14-3. Intel ICH3-S Layout Checklist (Sheet 2 of 4) Checklist Items Recommendations Comments LAN Interface General • Traces: 5 mils wide, 10 mil spacing. • Refer to Section 9.7. Guidelines • LAN Max Trace Length ICH3-S to CNR: •...
Page 218 Layout Checklist ® Table 14-3. Intel ICH3-S Layout Checklist (Sheet 3 of 4) Checklist Items Recommendations Comments LAN Interface (Continued) General • Vias to decoupling capacitors should be • To decrease series inductance. Guidelines sufficiently large in diameter. • Isolate I/O signals from high speed signals.
Page 219 Layout Checklist ® Table 14-3. Intel ICH3-S Layout Checklist (Sheet 4 of 4) Checklist Items Recommendations Comments General • RTC LEAD length = 0.25" Max. Guidelines • Minimize capacitance between RTCX1 and RTCX2. • Put GND plane underneath Crystal components.
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Page 221: Schematics
Schematics Schematics The E7500 Chipset Customer Reference Board schematics are attached. Note: Due to drawing tool capabilities, there are different representation of the voltage values throughout the schematics. i.e.,V3_3 implies the value of VCC3.3, V2_5 implies the value of VCC2.5, and so forth.
Page 222 Schematics This page is intentionally left blank. Design Guide...
Page 223 NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS. INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS...
Page 224 Voltage Regulators, Reset control....62-64 CK408B............65 FWH............66 SIO, Legacy I/O...........67,68 LAN..............69-71 SCSI............72-79 Front Panel Conn.........80 SMBus mux logic..........81 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering Spare gates, mounting holes......82 SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 225 Pages 49-52 Pages 67-68 Page 66 PCI-X Slot D extension Serial / PS2 KB/Mouse Floppy Parallel Simplified System Block Diagram TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 226 AB4, AD4, AA5 4,6,9 4,6,9 CPU_BPM2_N FSB_HD3_N AA25 4.7UH 4,6,9 CPU_BPM1_N FSB_HD2_N CPU1_VSSA 4,6,9 CPU_BPM0_N FSB_HD1_N AA27 FSB_HD0_N 33UF 4.7UH TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering CPU1_VCCIOPLL SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 227 VCC186 VSS90 VSS185 VCC92 VCC187 VSS91 VSS186 VCC93 VCC188 VSS92 VSS187 VCC94 VCC189 VSS93 VSS188 VCC95 VCC190 VSS94 VSS189 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 228 Caps close to pins FSB_HD4_N AD27 AB4, AD4, AA5 FSB_HD3_N AA25 4.7UH FSB_HD2_N CPU0_VSSA FSB_HD1_N AA27 FSB_HD0_N 33UF 4.7UH TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering CPU0_VCCIOPLL SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 229 THERMTRIP latch logic CPU_THRM_TRIP_N RSVD3 RSVD12 RSVD4 RSVD13 RSVD5 RSVD14 RSVD6 RSVD15 RSVD7 RSVD16 RSVD8 RSVD17 RSVD9 RSVD18 AE30 RSVD20 RSVD19 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 230 NOPOP NOPOP NOPOP NOPOP NOPOP NOPOP NOPOP NOPOP NOPOP C1475 C1476 C1477 C1478 560UF 560UF 560UF 560UF PROCESSOR DECOUPLING TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 231 J18 (Processor 0) ICH3_A20M_N 4,6,53 ICH3_IGNNE_N 4,6,53 ICH3_LINT0_INTR 4,6,53 CPU_LINT1_NMI 4,6,80 ICH3_CPUSLP_N 4,6,53 CPU0_SMI_N 6,80 CPU1_SMI_N 4,80 CPU_STPCLK_N 4,6,53 ICH3_INIT_N 4,6,53,66 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 232 +VCC_CPU +VCC_CPU 24.9 24.9 +V3_3 R776 MCH_XORMODE_N 4.7K Intel(R) E7500 Chipset Memory Controller Hub (MCH) System Bus I/F Data Group 0 Data Group 1 Data Group 2 Data Group 3 HDSTBP0_N DINV0_N HDSTBN0_N HDSTBP1_N DINV1_N HDSTBN1_N HDSTBP2_N DINV2_N HDSTBN2_N HDSTBP3_N...
Page 233 Hub Interface B MCH Hub Interfaces Hub Interface D Hub Interface C +V1_2 +V1_2 R105 R100 24.9 1% 24.9 R106 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 234 Command Clock Address Bus Chip Select C1143 0.1UF C1144 0.1UF C1145 0.1UF VREF_DDR_MCH 13,62 R115 6.81 MCH DDR Channel A TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 235 Command Clock Address Bus Chip Select C1146 0.1UF C1147 0.1UF C1148 0.1UF VREF_DDR_MCH 12,62 R120 6.81 MCH DDR Channel B TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 236 Place caps near DDR interface +VCC_CPU +V1_2 +V1_2 +VCC_CPU Near Hub interface Near FSB interface Backside caps near center of MCH TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 237 CAD Note: All Caps should have direct attatchment to 2.5V plane, and 2 vias to GND. 0.1uF Backside or Frontside Caps 6 caps between each pair of DIMMs TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED:...
Page 238 DDR DIMM C1149 0.1UF R128 R131 NOPOP 8.2K 8.2K R129 R130 NOPOP 8.2K 8.2K TITLE: R133 R132 INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS NOPOP 8.2K Platform Apps Engineering 8.2K SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 239 DDR DIMM C1150 0.1UF R137 R140 NOPOP 8.2K 8.2K R138 R139 NOPOP 8.2K 8.2K TITLE: R141 R142 INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS NOPOP 8.2K Platform Apps Engineering 8.2K SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 240 DDR DIMM C1151 0.1UF R143 R146 NOPOP 8.2K 8.2K R144 R145 8.2K 8.2K NOPOP R151 R150 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS NOPOP 8.2K 8.2K Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 241 DDR DIMM C1152 0.1UF R152 R155 NOPOP 8.2K 8.2K R153 R154 NOPOP 8.2K 8.2K TITLE: R160 R159 INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS NOPOP 8.2K Platform Apps Engineering 8.2K SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 242 Two Caps for each R-Pak VTT_DDR DDR Channel A Termination VTT_DDR VTT_DDR Two Caps for each R-Pak Two Caps for each R-Pak TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 243 CAD Note: All Caps should have direct attatchment 0.1uF Backside or Frontside Caps to 2.5V plane, and 2 vias to GND. 6 caps between each pair of DIMMs TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED:...
Page 244 DDR DIMM C1153 0.1UF R170 R169 NOPOP 8.2K 8.2K R167 R168 NOPOP 8.2K 8.2K R165 R166 NOPOP 8.2K TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS 8.2K Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 245 DDR DIMM C1154 0.1UF R177 R171 NOPOP 8.2K 8.2K R178 R179 NOPOP 8.2K 8.2K R172 R173 NOPOP 8.2K 8.2K TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 246 DDR DIMM C1155 0.1UF R186 R180 NOPOP 8.2K 8.2K R187 R188 NOPOP 8.2K 8.2K R181 R182 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS NOPOP 8.2K 8.2K Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 247 DDR DIMM C1156 0.1UF R195 R189 NOPOP 8.2K 8.2K R196 R197 NOPOP 8.2K 8.2K R190 R191 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS NOPOP 8.2K 8.2K Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 248 Two Caps for each R-Pak DDR Channel B Termination VTT_DDR VTT_DDR VTT_DDR Two Caps for each R-Pak Two Caps for each R-Pak TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 249 P64H2_1_HA_PRSNT1A 35,47 P64H2_1_PA_AD61 AC20 PA_AD61 PA_IRQ13_PRSNT2A P64H2_1_HA_PRSNT2A 35,47 P64H2_1_PA_AD62 AD20 PA_AD62 PA_IRQ14_FAULTA_N P64H2_1_HA_FAULTA_N P64H2_1_PA_AD63 PA_AD63 PA_IRQ15_SWITCHA P64H2_1_HA_SWITCHA P64H2 #1 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 250 28,35,69 P64H2_1_PB_AD60 PB_AD60 PB_IRQ12_PRSNT1A P64H2_1_HB_PRSNT1A P64H2_1_PB_AD61 PB_AD61 PB_IRQ13_PRSNT2A P64H2_1_HB_PRSNT2A P64H2_1_PB_AD62 PB_AD62 PB_IRQ14_FAULTA_N P64H2_1_HB_FAULTA_N P64H2_1_PB_AD63 PB_AD63 PB_IRQ15_SWITCHA P64H2_1_HB_SWITCHA P64H2 #1 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 251 P64H2 SMBus Address Strapping P64H2_1_PA_GNT4_N HPA_SIC_GNLEDB HPB_SIC_GNLEDB P64H2_1_HB_GNLEDB 8.2K Value 27,47 P64H2_1_HA_RESETA_N PA_GNT5_RESETA_N PA_GNT4_BUSENB_N PB_GNT5_RESETA_N PB_GNT4_BUSENB_N P64H2 #1 SMBus Address = C2h TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 252 P64H2 #1 power, ground and decoupling VCC1_8_39 VCC3_3_39 VCC1_8_40 VCC3_3_40 VCC3_3_41 VCC3_3_42 VCC3_3_43 VCC3_3_44 VCC3_3_45 VCC3_3_46 VCC3_3_47 VCC3_3_48 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS VCC3_3_49 Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 253 PA_AD60 PA_IRQ12_PRSNT1A P64H2_2_PA_IRQ12 P64H2_2_PA_AD61 AC20 PA_AD61 PA_IRQ13_PRSNT2A P64H2_2_PA_IRQ13 P64H2_2_PA_AD62 AD20 PA_AD62 PA_IRQ14_FAULTA_N P64H2_2_PA_IRQ14 P64H2_2_PA_AD63 PA_AD63 PA_IRQ15_SWITCHA P64H2_2_PA_IRQ15 P64H2 #2 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 254 P64H2_2_PB_IRQ12 36,46 P64H2_2_PB_AD61 PB_AD61 PB_IRQ13_PRSNT2A P64H2_2_PB_IRQ13 36,46 P64H2_2_PB_AD62 PB_AD62 PB_IRQ14_FAULTA_N P64H2_2_PB_IRQ14 36,46 P64H2_2_PB_AD63 PB_AD63 PB_IRQ15_SWITCHA P64H2_2_PB_IRQ15 36,46 P64H2 #2 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 255 P64H2_2_PA_GNT5_N HPB_SLOT[2:0] = 100b ==> Four hot-plug slots Value PA_GNT5_RESETA_N PA_GNT4_BUSENB_N PB_GNT5_RESETA_N PB_GNT4_BUSENB_N TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS P64H2 #2 SMBus Address = C0h Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 256 VCC1_8_36 VCC3_3_36 VCC1_8_37 VCC3_3_37 VCC1_8_38 VCC3_3_38 VCC1_8_39 VCC3_3_39 VCC1_8_40 VCC3_3_40 VCC3_3_41 VCC3_3_42 VCC3_3_43 VCC3_3_44 VCC3_3_45 VCC3_3_46 VCC3_3_47 VCC3_3_48 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS VCC3_3_49 Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 257 5.6K R1055 28,42,69 P64H2_1_PB_PERR_N 28,42,69 P64H2_1_PB_AD[63:0] 8.2K P64H2 #1 PCI Bus A pull-ups P64H2 #1 PCI Bus B pull-ups TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 258 8.2K P64H2_2_PA_AD32 P64H2_2_PB_AD34 8.2K 31,72 8.2K P64H2_2_PB_AD33 R268 P64H2_2_PA_AD[63:0] P64H2_2_PB_REQ5_N P64H2_2_PB_AD32 8.2K 32,43-46 8.2K P64H2_2_PB_AD[63:0] P64H2 #2 PCI pull-ups TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 259: Board Connector
SLOT_B_SWITCH SLOT_B_GRN_LED 37,38 SLOT_B_AMB_LED SLOT_A_SWITCH 37,38 SLOT_A_GRN_LED SLOT_A_AMB_LED Hot Plug logic, PCI-X Slots 1,2 Chassis hot-plug switch board connector TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 260 +V3_3 38,41 SLOT_C_CLKEN 74LVC00 SLOT_C_CLKEN_N SLOT_C_FAULT_N 38,41 74LVC00 SLOT_D_CLKEN SLOT_D_CLKEN_N SLOT_D_FAULT_N 38,41 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS 74LVC00 Hot Plug logic, PCI-X Slots A:D Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 261 SLOT_1_3V 0.005 SLOT_1_3V Route as diff pair PCI Hot Plug power controller 133Mhz (slot1) and 100Mhz (slot2) for P64H2#1 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 262 SLOT_B_3V_S SLOT_B_3V 44,50 SLOT_B_3V 0.005 Route as diff pair PCI Hot Plug power control. 66MHz Slots A and B TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 263 74LVC08 Route as diff pair PS_PWRGD_SLOT For Test Only PCI Hot Plug power control. 66MHz Slots C and D TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 264 CBT6810 SLOT_2_AD45 P64H2_1_PB_AD46 SLOT_2_AD44 P64H2_1_PB_AD45 SLOT_2_AD43 P64H2_1_PB_AD44 SLOT_2_AD42 P64H2_1_PB_AD43 TITLE: SLOT_2_BUSEN_N P64H2_1_PB_AD42 INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS 37,42 Slot 2 Hotplug bus switches U88_VBIAS SLOT_2_3V BIASV 39,42,48 Platform Apps Engineering R633 SHEET 1900 Prairie City Road CBT6820 LAST REVISED:...
Page 265 SLOT_A_3V 40,43,49 P64H2_2_PB_AD46 SLOT_A_AD46 P64H2_2_PB_AD45 SLOT_A_AD45 P64H2_2_PB_AD44 SLOT_A_AD44 P64H2_2_PB_AD43 SLOT_A_AD43 Slot A Hotplug bus switches P64H2_2_PB_AD42 SLOT_A_AD42 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS 2A10 2B10 Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 266 SLOT_B_3V 40,44,50 P64H2_2_PB_AD46 SLOT_B_AD46 P64H2_2_PB_AD45 SLOT_B_AD45 P64H2_2_PB_AD44 SLOT_B_AD44 P64H2_2_PB_AD43 SLOT_B_AD43 Slot B Hotplug bus switches P64H2_2_PB_AD42 SLOT_B_AD42 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS 2A10 2B10 Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 267 SLOT_C_3V 41,45,51 P64H2_2_PB_AD46 SLOT_C_AD46 P64H2_2_PB_AD45 SLOT_C_AD45 P64H2_2_PB_AD44 SLOT_C_AD44 P64H2_2_PB_AD43 SLOT_C_AD43 Slot C Hotplug bus switches P64H2_2_PB_AD42 SLOT_C_AD42 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS 2A10 2B10 Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 268 SLOT_D_3V 41,46,52 P64H2_2_PB_AD46 SLOT_D_AD46 P64H2_2_PB_AD45 SLOT_D_AD45 P64H2_2_PB_AD44 SLOT_D_AD44 P64H2_2_PB_AD43 SLOT_D_AD43 Slot D Hotplug bus switches TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS P64H2_2_PB_AD42 SLOT_D_AD42 2A10 2B10 Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 269 SLOT_1_12V 39,47 3_3V_T 3_3V_I P64H2_1_PA_ACK64_N P64H2_1_PA_REQ64_N 27,35 ACK64_N REQ64_N 27,35 +5V_G +5V_C +5V_H +5V_D continued 27,35,47 27,35,47 P64H2_1_PA_AD[63:0] TITLE: P64H2_1_PA_AD[63:0] INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 270 39,48 39,48 SLOT_2_AD1 SLOT_2_AD0 3_3V_T 3_3V_I SLOT_2_ACK64_N SLOT_2_REQ64_N ACK64_N REQ64_N +5V_G +5V_C +5V_H +5V_D continued 42,48 42,48 SLOT_2_AD[63:0] TITLE: SLOT_2_AD[63:0] INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 271 40,49 40,49 SLOT_A_AD1 SLOT_A_AD0 3_3V_T 3_3V_I SLOT_A_ACK64_N SLOT_A_REQ64_N ACK64_N REQ64_N +5V_G +5V_C +5V_H +5V_D continued 43,49 43,49 SLOT_A_AD[63:0] TITLE: SLOT_A_AD[63:0] INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 272 SLOT_B_M12V SLOT_B_12V 40,50 40,50 3_3V_T 3_3V_I SLOT_B_ACK64_N SLOT_B_REQ64_N ACK64_N REQ64_N +5V_G +5V_C +5V_H +5V_D continued 44,50 44,50 SLOT_B_AD[63:0] TITLE: SLOT_B_AD[63:0] INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 273 41,51 41,51 SLOT_C_AD1 SLOT_C_AD0 3_3V_T 3_3V_I SLOT_C_ACK64_N SLOT_C_REQ64_N ACK64_N REQ64_N +5V_G +5V_C +5V_H +5V_D continued 45,51 45,51 SLOT_C_AD[63:0] TITLE: SLOT_C_AD[63:0] INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 274 11,52 SLOT_D_HI[15:0] GND_16 B129 GND_15 A129 11,52 SLOT_D_HI[15:0] TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET PCI-X 66MHz SLOT D (Hub Interface Extension for Test Purposes Only) 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 275 REQ2_N LANCLK ICH3_REQ3_N REQ3_N LANRXD0 ICH3_REQ4_N REQ4_N LANRXD1 ICH3_GNT0_N GNT0_N LANRXD2 GNT1_N LANRSTSYNC GNT2_N LANTXD0 GNT3_N LANTXD1 GNT4_N LANTXD2 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 276 USBLEDG1_N_GPIO39 SDD10 AC16 USBLEDG2_N_GPIO40 SDD11 AB17 USBLEDG3_N_GPIO41 SDD12 AA17 USBLEDG4_N_GPIO42 SDD13 USBLEDG5_N_GPIO43 SDD14 R374 ICH3_USB_RBIAS AC18 USBRBIAS SDD15 18.2 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 277 VCCSUS1_8_6 +V3_3 VCCSUS1_8_7 BAV70LT1 VCCSUS1_8_8 VCCSUS1_8_9 VCCSUS1_8_10 VCCSUS1_8_11 +VCC_CPU VCCSUS1_8_12 VCCSUS1_8_13 V_CPU_IO_1 SPST Switch V_CPU_IO_2 V_CPU_IO_3 ICH3_PWRBTN_N 55,80 PWR_BTN TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 278 USB connector ICH3_USB_OC1_N 50 OHMS ICH3_USBP1N CONN_USBP1_N FB13 50 OHMS ICH3_USBP1P CONN_USBP1_P FB14 USB Connectors TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 279 C/BE0- ICH3_AD7 +3.3V ICH3_AD6 +3.3V ICH3_AD4 ICH3_AD5 ICH3_AD3 ICH3_AD2 ICH3_AD[31:0] ICH3_AD0 ICH3_AD1 53,57,58 53,57,58 ICH3_AD[31:0] PCI33_REQ64_N PCI33_ACK64_N REQ64- ACK64- TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 280 R467 VSYNC VGA_DDCDAT CON_VSYNC 60 OHMS GND0 VGA_HSYNC 60 OHMS GND4 VGA_VSYNC FB28 R466 VGA_DDCCLK CON_DDCCLK FB29 Onboard Video TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 281 R475 4.7K Asiliant* 69000 R474 Onboard Video TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 282 CPU0_VID1 CPU1_VID[4:0] CPU1_VID4 4,60 CPU0_VID0 +V3_3 CPU1_VID3 CPU1_VID2 CPU1_VID1 CPU_OK VRD_ON_N PS_PWRGD_SYS 64,80 74LVC00 R649 VRD Enable logic CPU1_VID0 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 283 6301_PWM3 6301_PWM2 LGATE LGATE LGATE NOPOP C456 C1511 100PF NOPOP C458 C459 6301_ISEN4 6301_ISEN3 6301_ISEN2 Processor Voltage Regulator circuitry TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 284 Small Signal Ground originating near DIMMs Route as diff pair Place between VR pins 13, 14 Drive Power Ground TITLE: V2_5SENSE2_P INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS V2_5SENSE2_M 1929_VOS_P Platform Apps Engineering 1929_VOS_M SHEET DDR V2_5 Regulation 1900 Prairie City Road...
Page 285 EXTVCC U115 Route as C1552 Small Signal diff pair Ground 0.1UF V1_2SENSE_P V1_2SENSE_N C1560 Place C1560 between pins 5,6 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 286 PWROK generation 29,33,55 74LVC14 R771 Standby supply monitor 1929_PGOOD PWROK_RST_N R768 VTT_DDR_PGOOD SPST Switch R770 RST_PD R976 RESET_BTN DBR_RESET_N TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 287: Clock Synthesizer
16-19,22-25,80,81 CK408_VTT_PWRGD_N I2C_BUS3_DAT VTT_PWRGD_N SDATA 16-19,22-25,80,81 +V3_3 V3_CLK CAD Note: Ground flood around CK-408B. 30 OHMS CK408B Clock Synthesizer TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 288 R485 FGPI0 FWH_FGP_10 4.7K INIT FWH_INIT_N 673755-002 VCCA TP_FWH_03_6 VCC0 VCC1 2N3904_DUAL R484 GNDA ICH3_INIT_N R_ICH3_INIT_N 4,6,9,53 GND0 GND1 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 289 HDSEL_N HDSEL~ +V5_0 +VSBY3_3 +V3_3 INDEX_N INDEX~ TRK0_N TRK0~ WRTPRT_N WRTPRT~ RDATA_N RDATA~ DSKCHG_N DSKCHG~ ICH3_SUSCLK CLKI32 CLK_14MHZ_SIO CLOCKI TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 290 HDSEL_N LPT_PD2 LPT_PD2_R DSKCHG_N LPT_INIT_N LPT_INIT_N_R RP205 RP209 LPT_PD1 LPT_PD1_R LPT_PD0 LPT_PD0_R LPT_ALF_N LPT_ALF_N_R LPT_STROBE_N LPT_STROBE_N_R DB-25 R559 LPT_ERROR_N TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 291 Other Signals PHY Signals +V3_3 +V3_3 R660 25.000MHZ +V3_3 34.8 EEPROM LINK_UP_N LINK_ACT_N AT93C46 U101 LINK100_N 3.3V part only TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS LINK1000_N Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 292 NC29 AE22 VSS65 VSS127 NC14 NC30 AF22 VSS128 NC15 NC31 AF25 AF23 VSS129 NC16 NC32 AF26 VSS130 NC34 NC33 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 293 +V2_5 MDC1 MDXC1 MDC2 MDXC2 MDC3 MDXC3 SO24-CUST RJ45_P10 RJ45_P12 C1626 LAN_AGND 70,71 1500PF LAN EEPROM, Magnetics and Connector TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 294 SCSI_SEEDO SCSI_SEEDI See Adaptec* AIC-7902 Design-In Handbook for up-to-date information regarding implementation of this subsystem C1312 0.01UF TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS SCSI Controller Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 295 R685 R683 4.7K 4.7K See Adaptec* AIC-7902 Design-In Handbook for up-to-date information regarding implementation of this subsystem SCSI Controller TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 296 10UF 10UF SCSI PWR/GND See Adaptec* AIC-7902 Design-In Handbook for up-to-date information regarding implementation of this subsystem SCSI Controller TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 297 AB15 VIO_6 AB16 TEST_4 VIO_7 AB19 TEST_5 VIO_8 AB20 TEST_6 VIO_9 TEST_7 TEST_8 TEST0 TEST_9 TEST1 TEST3 SCSI Controller TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 298 OUT+ AIC_CLKNP A2920OSC OUT- AIC_CLKNM OSC_80MHZ See Adaptec* AIC-7902 Design-In Handbook for TITLE: up-to-date information regarding implementation of this subsystem INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 299 LVSCDBP11 LVSCDBM11 73,78 73,78 73,79 73,79 See Adaptec* AIC-7902 Design-In Handbook for up-to-date information regarding implementation of this subsystem TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 300 DIFF_CAP HSGND2 HSGND1 VREF 20 MIL trace See Adaptec* AIC-7902 Design-In Handbook for TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS up-to-date information regarding implementation of this subsystem Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: 20MIL Folsom, California 095630...
Page 301 DIFF_CAP HSGND2 HSGND1 VREF 20 MIL trace See Adaptec* AIC-7902 Design-In Handbook for TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS up-to-date information regarding implementation of this subsystem Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: 20MIL Folsom, California 095630...
Page 302 CPU_PROC_HOT_N +VSBY5_0 +VSBY5_0 CPU1_SKTOCC_N CPU0_SKTOCC_N PS_ON_N CONN_PS_ON_N Pull-ups for fan tach on fan cntl board For Test Purposes Only TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 303 4,6,11,80,81 I2C_BUS0_CLK 60,80,81 I2C_BUS2_CLK 4,6,11,80,81 JP38 JP40 SMBUS_1_V3_3 SMBUS_3_V3_3 I2C_BUS1_DAT 29,33,42,44,45,80,81 I2C_BUS3_DAT 16-19,22-25,65,80,81 I2C_BUS1_CLK 29,33,42,44,45,80,81 I2C_BUS3_CLK 16-19,22-25,65,80,81 JP39 JP41 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 304 FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FID31 FID32 FID34 FID33 FID36 FID35 FID38 FID37 FID40 FID39 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...
Page 305 SMB Slave Address = 88h ICH3_SMBUS_SEL0 GPIO27 ICH3_SMBUS_SEL1 GPIO28 TITLE: INTEL(R) E7500 CHIPSET CUSTOMER REFERENCE SCHEMATICS SMBUS PARTITION MAP Platform Apps Engineering SHEET 1900 Prairie City Road LAST REVISED: Folsom, California 095630 03/04/02...

Intel Xeon Design Manual

Introduction

Component Quadrant Layout

Platform Stack-Up and Component Placement Overview

Platform Clock Routing Guidelines

System Bus Routing Guidelines

Memory Interface Routing Guidelines

Hub Interface

82870P2 (P64H2)

I/O Controller Hub

Quick Links

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Summary of Contents for Intel Xeon