Intel ARM Cortex-A9 Introduction Manual
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Intel ARM Cortex-A9 Introduction Manual

Intel ARM Cortex-A9 Introduction Manual

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For Quartus Prime 16.1
1 Introduction
This tutorial presents an introduction to the ARM
hardware block in Intel's Cyclone
ARM-based system on Intel's DE1-SOC board.
A full description of ARM processors is provided in the ARM Architecture Reference Manual, which is available on
the ARM Holdings web site.
Contents:
• Overview of ARM Cortex-A9 Processor Features
• Register Structure
• Instruction Sets
• Accessing Memory and I/O Devices
• Addressing Modes
• ARM Instructions
• Assembler Directives
• Example Program
• Operating Modes
• Banked Registers
• Exception Processing
• Input/Output Operations
Intel Corporation - FPGA University Program
November 2016
®
Cortex-A9 processor, which is a processor implemented as a
®
V SoC FPGA devices. The tutorial is intended for a user who wishes to use an
Introduction to the ARM
Using Intel FPGA Toolchain
®
Processor
1

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Summary of Contents for Intel ARM Cortex-A9

  • Page 1 A full description of ARM processors is provided in the ARM Architecture Reference Manual, which is available on the ARM Holdings web site. Contents: • Overview of ARM Cortex-A9 Processor Features • Register Structure • Instruction Sets • Accessing Memory and I/O Devices •...

  • Page 2: Register Structure

    3 Register Structure All registers in the ARM Cortex-A9 processor are 32 bits long. There are 15 general-purpose registers, R0 to R14, a Program Counter, R15, and a Current Program Status Register, CPSR, as shown in Figure 1. All general-purpose registers can be used in the same way.

  • Page 3: Instruction Sets

    Section 10. 4 Instruction Sets The ARM Cortex-A9 processor can execute instructions in three different instruction sets, known as ARM, Thumb and Thumb-2. The ARM set is the most powerful. All instructions are 32 bits long. The instructions are stored in memory in word-aligned manner.
  • Page 4 . This makes it possible to access memory locations in terms of their distance relative to the current address in R15. This mode is often referred to as the Relative addressing mode. Intel Corporation - FPGA University Program November 2016...
  • Page 5 R2 from the address in R6 minus 8. The instruction LDR R2, [R6, #0x200] loads R2 from the address in R6 plus the hexadecimal number 0x200. The instruction LDR R2, [R6, R8] Intel Corporation - FPGA University Program November 2016...
  • Page 6 Observe, in Figure 2, that the high-order four bits denote a condition for the instruction. In ARM processors, most instructions can be executed conditionally, as explained in Section 6.11. Intel Corporation - FPGA University Program November 2016...

  • Page 7: Load And Store Instructions

    8- or 16-bit value to 32 bits in the LDRB and LDRH instructions. In the LDRSB and LDRSH instructions the operand is sign-extended. The corresponding Store instructions are: • STRB (Store Register Byte) Intel Corporation - FPGA University Program November 2016...
  • Page 8 R4, R6, R7, R8 and R10. If the starting address in R3 is 1000, then the data loaded into the registers will be from addresses 1000, 1004, 1008, 1012 and 1016, respectively. Because the Pre-indexed mode is specified, the final contents of R3 will be 1020. Intel Corporation - FPGA University Program November 2016...

  • Page 9: Data Processing Instructions

    This instruction performs the operation OP using the contents of R and the constant value, and places the result into R . For example, if OP is the addition instruction ADD, then ADD R0, R1, #1 Intel Corporation - FPGA University Program November 2016...
  • Page 10 An optional cond appended to an instruction mnemonic allows an instruction to be either executed or skipped, depending on the current values of the condition code flags. This concept is discussed in Section 6.10. Intel Corporation - FPGA University Program November 2016...

  • Page 11: Arithmetic Instructions

    Thus, MLA R2, R4, R5, R6 multiplies the numbers in R4 and R5, adds to this product the number in R6, and places the result into register R2. Intel Corporation - FPGA University Program November 2016...

  • Page 12: Move Instructions

    , Operand2 moves the value of Operand2 into register R The Move Negative instruction MVN R , Operand2 moves the complement of the value of Operand2 into R The Move Top instruction Intel Corporation - FPGA University Program November 2016...

  • Page 13: Shift And Rotate Instructions

    R5 to the left by four bit-positions (zeros are inserted on the right) and places the result into R2. Since Operand2 of any instruction can be shifted or rotated, it is possible to use Move instructions mnemonics instead of shift and rotate. For example, the instruction Intel Corporation - FPGA University Program November 2016...

  • Page 14: Comparison Instructions

    The data processing instructions (arithmetic, logic and move) affect these flags if the suffix S is appended to the assembly-language OP-code mnemonic, as we mentioned in Section 6.3.1. For example, the instruction Intel Corporation - FPGA University Program November 2016...

  • Page 15: Branch Instructions

    6.11 Branch Instructions The flow of execution of a program can be changed by executing a Branch instruction. It may be changed either conditionally or unconditionally. A branch instruction is specified as Intel Corporation - FPGA University Program November 2016...
  • Page 16 1 1 0 0 Signed greater than Z (N V) 1 1 0 1 Signed less than or equal Z (N V) 1 1 1 0 Always 1 1 1 1 not used Intel Corporation - FPGA University Program November 2016...

  • Page 17: Assembler Directives

    We will restrict our discussion to the assembler that is used by the Intel FPGA Monitor Program. This assembler conforms to the widely used GNU Assembler, which is software available in the public domain. Thus, the GNU Assembler directives can be used in ARM programs intended to be used with the Intel FPGA Monitor Program.
  • Page 18 Identifies the code that should be placed in the text section of the memory. The desired memory location for the text section can be specified in the Monitor Program’s system configuration window. .word expressions Expressions separated by commas are specified. Each expression is assembled into a 32-bit number. Intel Corporation - FPGA University Program November 2016...

  • Page 19: Example Program

    /* Space for the final dot product. */ .end Figure 3. A program that computes the dot product of two vectors. Observe the treatment of labels. In the instruction LDR R0, AVECTOR Intel Corporation - FPGA University Program November 2016...

  • Page 20: Operating Modes

    Figure 1. Other modes, which deal with various exceptions, use some other registers, as described in the next section. The current operating mode is indicated in the processor status bits CPSR , as specified in Table 3. Intel Corporation - FPGA University Program November 2016...
  • Page 21 All exception modes use their own versions of the Stack Pointer, SP_mode, the Link register, LR_mode, and the Status register, SPSR_mode. The FIQ mode also has its own registers R8 to R12, which are called R8_fiq to R12_fiq in the figure. Intel Corporation - FPGA University Program November 2016...
  • Page 22 CPSR In the Supervisor mode, the special Move instructions, MRS and MSR, can be used to access the processor status registers CPSR and SPSR_svc. The instruction MRS R , CPSR Intel Corporation - FPGA University Program November 2016...

  • Page 23: Exception Processing

    • Attempted accessing of a nonexistent memory location • Unimplemented instruction The ARM Cortex-A9 processor uses a vectored exception scheme, in which there is a separate vector of information assigned to each type of exception. This vector normally consists of an instruction that loads into the program counter the address of the first instruction of the corresponding exception-service routine.

  • Page 24: Software Interrupt

    PC, a return to the interrupted program is completed. A common use of the software interrupt is to transfer control to a different program, such as an operating system. Intel Corporation - FPGA University Program November 2016...

  • Page 25: Hardware Interrupts

    first having to save the contents of R8 to R12 on the stack. This leads to a faster response. The return from the exception-service routine should be performed with the instruction Intel Corporation - FPGA University Program November 2016...
  • Page 26 The following example shows how the exception vector table can be set up, and how the exception-service routines can be organized. We will use a hardware IRQ interrupt as an example of an exception-service routine. Intel Corporation - FPGA University Program November 2016...
  • Page 27 /* Return to interrupted program. */ /* Service routine for software interrupts. */ SERVICE_SVC: MOVS PC, LR /* Return to interrupted program. */ Figure 5. Code used to set up the exception processing. Intel Corporation - FPGA University Program November 2016...

  • Page 28: Input/Output Operations

    (MMU) is set up such that appropriate regions of memory are designated as non-cacheable. The procedure for setting up the MMU and data cache is beyond the scope of this document. Intel Corporation - FPGA University Program November 2016...
  • Page 29 Intel warrants performance of its semiconductor products to current specifications in accordance with Intel’s stan- dard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel Corporation.

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