Rx Write Logic; Dbg_Sr[0]; Flush_Rr; Hs_Download - Intel XScale Core Developer's Manual

9.11.3.1

RX Write Logic

The RX write logic
1) RX Write Enable: The RX register only gets updated when rx_valid is set and is unaffected
if rx_valid is clear or an overflow occurs. In particular, when the debugger is polling
DBG_SR[0], as long as rx_valid is 0, Update_DR does not modify RX.
2) Set TXRXCTRL.RR: When the debugger writes new data to RX, TXRXCTRL.RR is
automatically set signalling to the debug handler that the RX register contains valid data.
3) Set TXRXCTRL.OV: When the debugger scans in a value with rx_valid set and
TXRXCTRL.RR is already set, the TXRXCTRL.OV is automatically set. For instance, during
high-speed download, the debugger does not poll to see if the handler has read the previous
data. If the debug handler stalls long enough, the debugger may try to write a new data to RX
before the handler has read the previous data. When this condition is occurs, the RX write
logic sets TXRXCTRL.OV and blocks the write to the RX register.
9.11.3.2

DBG_SR[0]

DBG_SR[0] is used for part of the synchronization that occurs between the debugger and debug
handler for accessing RX. The debugger polls DBG_SR[0] to determine when the handler has read
the previous data from RX, and it is safe to write new data.
A '1' read in DBG_SR[0] indicates that the RX register contains valid data which has not yet been
read by the debug handler. A '0' indicates it is safe for the debugger to write new data to the RX
register.
9.11.3.3

flush_rr

The flush_rr bit allows the debugger to flush any previous data written to RX. Setting flush_rr
clears TXRXCTRL.RR.
9.11.3.4

hs_download

The hs_download bit is provided for use during high speed download. This bit is written directly to
TXRXCTRL.D. The debugger can use this bit to improve performance when downloading a block
of code or data to the Elkhart system memory.
A protocol can be setup between the debugger and debug handler using this bit. For example, while
this bit is set, the debugger can continuously download new data without polling TXRXCTRL.RR.
The debug handler uses TXRXCTRL.D as a branch flag to loop while there is more data to come.
The debugger clears this bit to indicate the end of the block and allow the debug handler to exit its
loop.
Using hs_download as a branch flags eliminates the need for a loop counter in the debug handler
code. This avoids the problem were the debugger's loop counter is out of synchronization with the
debug handler's counter because of overflow conditions that may have occurred.
9.11.3.5

RX (DBG_SR[34:3])

DBG_SR[34:3] is written to RX following an Update_DR when the RX Write Logic enables the
RX register to be updated.
Developer's Manual
(Figure 9-3) serves the following functions:
January, 2004
Intel XScale® Core Developer's Manual
Software Debug
143