Intel XScale Core Developer's Manual page 9

A.4.4.6. Bandwidth Limitations .......................................................................... 200
A.4.4.7. Cache Memory Considerations............................................................ 201
A.4.4.8. Cache Blocking .................................................................................... 203
A.4.4.9. Prefetch Unrolling ................................................................................ 203
A.4.4.10. Pointer Prefetch ...................................................................................204
A.4.4.11. Loop Interchange ................................................................................. 205
A.4.4.12. Loop Fusion ......................................................................................... 205
A.4.4.13. Prefetch to Reduce Register Pressure ................................................ 206
A.5 Instruction Scheduling ......................................................................................................207
A.5.1 Scheduling Loads ................................................................................................ 207
A.5.1.1. Scheduling Load and Store Double (LDRD/STRD) ............................. 210
A.5.1.2. Scheduling Load and Store Multiple (LDM/STM)................................. 211
A.5.2 Scheduling Data Processing Instructions ............................................................ 212
A.5.3 Scheduling Multiply Instructions .......................................................................... 213
A.5.4 Scheduling SWP and SWPB Instructions ............................................................ 214
A.5.5 Scheduling the MRA and MAR Instructions (MRRC/MCRR)...............................215
A.5.6 Scheduling the MIA and MIAPH Instructions ....................................................... 216
A.5.7 Scheduling MRS and MSR Instructions............................................................... 217
A.5.8 Scheduling CP15 Coprocessor Instructions ........................................................ 217
A.6 Optimizing C Libraries ......................................................................................................218
A.7 Optimizations for Size ....................................................................................................... 218
A.7.1 Space/Performance Trade Off ............................................................................. 218
A.7.1.1. Multiple Word Load and Store ............................................................. 218
A.7.1.2. Use of Conditional Instructions ............................................................ 218
A.7.1.3. Use of PLD Instructions .......................................................................218
B Test Features .............................................................................................................................. 219
B.1 Overview ........................................................................................................................... 219
Developer's Manual
Intel XScale® Core Developer's Manual
January, 2004
Contents
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