Trace Buffer; Trace Buffer Registers - Intel XScale Core Developer's Manual

9.12

Trace Buffer

The 256 entry trace buffer provides the ability to capture control flow information to be used for
debugging an application. Two modes are supported:
1. The buffer fills up completely and generates a debug exception. Then SW empties the buffer.
2. The buffer fills up and wraps around until it is disabled. Then SW empties the buffer.
9.12.1

Trace Buffer Registers

CP14 contains three registers (see
are accessible using MRC, MCR, LDC and STC (CDP to any CP14 registers will cause an
undefined instruction trap). The CRn and CRm fields specify the register to access. The opcode_1
and opcode_2 fields are not used and should be set to 0.
Table 9-15. CP 14 Trace Buffer Register Summary
CRn
11
12
13
Any access to the trace buffer registers in User mode will cause an undefined instruction exception.
Specifying registers which do not exist has unpredictable results.
Developer's Manual
Intel XScale® Core Developer's Manual
Table 9-15) for use with the trace buffer. These CP14 registers
CRm
0 Trace Buffer Register (TBREG)
0 Checkpoint 0 Register (CHKPT0)
0 Checkpoint 1 Register (CHKPT1)
January, 2004
Software Debug
Register Name
145