Introduction; About This Document; How To Read This Document - Intel XScale Core Developer's Manual

Introduction

1.1

About This Document

This document is the authoritative and definitive reference for the external architecture of the Intel
®
XScale
This document describes two variants of the Intel XScale
monitoring and the size of the JTAG instruction register. Software can detect which variant it is
running on by examining the CoreGen field of Coprocessor 15, ID Register (bits 15:13). (See
Table 7-4, "ID Register" on page 7-81
XSC1 and a value of 0x2 is referred to as XSC2.
Intel Corporation assumes no responsibility for any errors which may appear in this document nor
does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice. In
particular, descriptions of features, timings, and pin-outs does not imply a commitment to
implement them.
1.1.1

How to Read This Document

It is necessary to be familiar with the ARM Version 5TE Architecture in order to understand some
aspects of this document.
Each chapter in this document focuses on a specific architectural feature of the Intel XScale
•
Chapter 2, "Programming Model"
•
Chapter 3, "Memory Management"
•
Chapter 4, "Instruction Cache"
•
Chapter 5, "Branch Target Buffer"
•
Chapter 6, "Data Cache"
•
Chapter 7, "Configuration"
•
Chapter 8, "Performance Monitoring"
•
Chapter 9, "Software Debug"
•
Chapter 10, "Performance Considerations"
Several appendices are also present:
•
Appendix A, "Optimization Guide"
•
Appendix B, "Test Features"
Note: All the "buzz words" and acronyms found throughout this document are captured in
"Terminology and Acronyms" on page
1. ARM* architecture compliant.
Developer's Manual
1
core .
describes the JTAG unit.
January, 2004
Intel XScale® Core Developer's Manual
®
core that differ only in the performance
for more details.) A CoreGen value of 0x1 is referred to as
covers instruction scheduling techniques.
1-19, located at the end of this chapter.
Introduction
1
®
core.
Section 1.3.2,
13