Instruction Cache Control; Instruction Cache State At Reset; Enabling/Disabling - Intel XScale Core Developer's Manual

Intel XScale® Core Developer's Manual
Instruction Cache
4.3

Instruction Cache Control

4.3.1

Instruction Cache State at RESET

After reset, the instruction cache is always disabled, unlocked, and invalidated (flushed).
4.3.2

Enabling/Disabling

The instruction cache is enabled by setting bit 12 in coprocessor 15, register 1 (Control Register).
This process is illustrated in
Example 4-2. Enabling the Instruction Cache
; Enable the ICache
MRC P15, 0, R0, C1, C0, 0
ORR R0, R0, #0x1000
MCR P15, 0, R0, C1, C0, 0
CPWAIT
52
Example 4-2, Enabling the Instruction
; Get the control register
; set bit 12 -- the I bit
; Set the control register
January, 2004
Cache.
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