High-Level Overview Of The Intel Xscale ® Core; Arm Compatibility - Intel XScale Core Developer's Manual

1.2 High-Level Overview of the Intel XScale
The Intel XScale
performance and low-power; leading the industry in mW/MIPs. The core is not intended to be
delivered as a stand alone product but as a building block for an ASSP (Application Specific
Standard Product) with embedded markets such as handheld devices, networking, storage, remote
access servers, etc.
The Intel XScale
achieve high performance. This rich feature set allows programmers to select the appropriate
features that obtains the best performance for their application. Many of the architectural features
added to the Intel XScale
high performance processors. This includes:
•
the ability to continue instruction execution even while the data cache is retrieving data from
external memory.
•
a write buffer.
•
write-back caching.
•
various data cache allocation policies which can be configured different for each application.
•
and cache locking.
All these features improve the efficiency of the memory bus external to the core.
The Intel XScale
support of 16-bit data types and 16-bit operations. These audio coding enhancements center around
multiply and accumulate operations which accelerate many of the audio filter operations.
1.2.1

ARM Compatibility

ARM Version 5 (V5) Architecture added floating point instructions to ARM Version 4. The Intel
®
XScale
hardware support of the floating point instructions.
The Intel XScale
extensions.
Backward compatibility with StrongARM* products is maintained for user-mode applications.
Operating systems may require modifications to match the specific hardware features of the Intel
®
XScale
Developer's Manual
®
core is an ARM V5TE compliant microprocessor. It has been designed for high
®
core incorporates an extensive list of architecture features that allows it to
®
core help hide memory latency which often is a serious impediment to
®
core has been equipped to efficiently handle audio processing through the
core implements the integer instruction set architecture of ARM V5, but does not provide
®
core provides the Thumb instruction set (ARM V5T) and the ARM V5E DSP
core and to take advantage of the performance enhancements added.
January, 2004
Intel XScale® Core Developer's Manual
®
Introduction
Core
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