Steps For Loading Mini Instruction Cache During Reset - Intel XScale Core Developer's Manual

Table 9-20
during reset:
Table 9-20.

Steps For Loading Mini Instruction Cache During Reset

Step #
1 Assert Chip Reset and Chip TRST
2 Read ID Register value
Program SELDCSR JTAG register:
Halt Mode=1
3
Trap Reset=1
hold_reset=1
4 Deassert Chip Reset
5 Wait N TCKs
Program SELDCSR JTAG register:
Halt Mode=1
6
Trap Reset=1
hold_reset=1
Load LDIC JTAG instruction and
7 download the debug handler into
mini instruction cache.
Clock a minimum of 20 TCKs
8
before changing the JTAG IR.
Program SELDCSR JTAG register:
Halt Mode bit = 1
9
Trap Reset bit = 1
hold_reset = 0
10 poll the DBGTX register
Developer's Manual
describes the actions a debugger should take to load code into the mini instruction cache
Action
January, 2004
Intel XScale® Core Developer's Manual
Notes
This resets the JTAG IR to IDCODE and clears the Halt Mode
bit in the DCSR, ensuring that the main and mini IC are
invalidated.
SELDCSR details can be found in
Depending on ASSP implementation, the Halt Mode bit and
Trap Reset bit may or may not actually be set to the
programmed value. The hold reset bit will be set to the
programmed value.
Internally the core will remain held in reset due to hold_reset
being set.
N is a ASSP specific number and can be found in the
Implementations options section of the ASSP architecture
specification. This wait ensures that the core is stable before
proceeding.
The SELDCSR instruction must be reloaded into the JTAG IR.
Failure to reload the JTAG IR may result in unpredictable
behavior.
Reprogramming of the SELDCSR JTAG register guarantees
that the Halt Mode bit and Trap Reset bit are set before loading
the mini instruction cache.
Loading into the instruction cache is described in
Section 9.14.4, "LDIC Cache Functions"
The LDIC JTAG instruction must remain in the JTAG instruction
register for at least 20 TCKs following the update_dr for the last
cache line, to ensure that line is correctly loaded into the mini
instruction cache. Changing the JTAG IR within 20 cycles my
result in unpredictable behavior.
Clearing the hold_reset bit allows the core to come out of reset
and begin execution from address 0.
Immediately out of reset, a reset vector trap will occur and the
debug handler will begin execution. The debugger must poll
DBGTX to identify when this has happened.
Software Debug
Section 9.11.1.
159