Xsc2 Performance Monitoring Registers; Accessing The Xsc2 Performance Monitoring Registers - Intel XScale Core Developer's Manual

7.3.1.2

XSC2 Performance Monitoring Registers

The performance monitoring unit in XSC2 contains a control register (PMNC), a clock counter
(CCNT), interrupt enable register (INTEN), overflow flag register (FLAG), event selection register
(EVTSEL) and four event counters (PMN0 through PMN3). The format of these registers can be
found in Chapter 8, "Performance
performance monitoring facility.
Opcode_2 should be zero on all accesses.
These registers can't be accessed by LDC and STC coprocessor instructions.
Table 7-22.

Accessing the XSC2 Performance Monitoring Registers

(PMNC) Performance Monitor Control
Register
(CCNT) Clock Counter Register
(INTEN) Interrupt Enable Register
(FLAG) Overflow Flag Register
(EVTSEL) Event Selection Register
(PMN0) Performance Count Register 0
(PMN1) Performance Count Register 1
(PMN2) Performance Count Register 2
(PMN3) Performance Count Register 3
Developer's Manual
Monitoring", along with a description on how to use the
Description
January, 2004
Intel XScale® Core Developer's Manual
CRn CRm
Register# Register#
Read: MRC p14, 0, Rd, c0, c1, 0
0b0000 0b0001
Write: MCR p14, 0, Rd, c0, c1, 0
Read: MRC p14, 0, Rd, c1, c1, 0
0b0001 0b0001
Write: MCR p14, 0, Rd, c1, c1, 0
Read: MRC p14, 0, Rd, c4, c1, 0
0b0100 0b0001
Write: MCR p14, 0, Rd, c4, c1, 0
Read: MRC p14, 0, Rd, c5, c1, 0
0b0101 0b0001
Write: MCR p14, 0, Rd, c5, c1, 0
Read: MRC p14, 0, Rd, c8, c1, 0
0b1000 0b0001
Write: MCR p14, 0, Rd, c8, c1, 0
Read: MRC p14, 0, Rd, c0, c2, 0
0b0000 0b0010
Write: MCR p14, 0, Rd, c0, c2, 0
Read: MRC p14, 0, Rd, c1, c2, 0
0b0001 0b0010
Write: MCR p14, 0, Rd, c1, c2, 0
Read: MRC p14, 0, Rd, c2, c2, 0
0b0010 0b0010
Write: MCR p14, 0, Rd, c2, c2, 0
Read: MRC p14, 0, Rd, c3, c2, 0
0b0011 0b0010
Write: MCR p14, 0, Rd, c3, c2, 0
Configuration
Instruction
97