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1.3
Terminology and Conventions
1.3.1
Number Representation
All numbers in this document can be assumed to be base 10 unless designated otherwise. In text and
pseudo code descriptions, hexadecimal numbers have a prefix of 0x and binary numbers have a prefix
of 0b. For example, 107 would be represented as 0x6B in hexadecimal and 0b1101011 in binary.
1.3.2
Terminology and Acronyms
ASSP
Assert
BTB
Clean
Coalescing
Deassert
Flush
XSC1
XSC2
Reserved
Developer's Manual
Application Specific Standard Product
This term refers to the logically active value of a signal or bit.
Branch Target Buffer
A clean operation updates external memory with the contents of the specified line in
the data/mini-data cache if any of the dirty bits are set and the line is valid. There are
two dirty bits associated with each line in the cache so only the portion that is dirty
will get written back to external memory.
After this operation, the line is still valid and both dirty bits are deasserted.
Coalescing means bringing together a new store operation with an existing store
operation already resident in the write buffer. The new store is placed in the same
write buffer entry as an existing store when the address of the new store falls in the
4 word aligned address of the existing entry. This includes, in PCI terminology, write
merging, write collapsing, and write combining.
This term refers to the logically inactive value of a signal or bit.
A flush operation invalidates the location(s) in the cache by deasserting the valid bit.
Individual entries (lines) may be flushed or the entire cache may be flushed with one
command. Once an entry is flushed in the cache it can no longer be used by the
program.
XSC1 refers to a variant of the Intel XScale
(Coprocessor 15, ID Register) value of 0x1. This variant has a 2 counter performance
monitor and a 5-bit JTAG instruction register. See
page 7-81
for more details.
XSC2 refers to a variant of the Intel XScale
(Coprocessor 15, ID Register) value of 0x2. This variant has a 4 counter performance
monitor and a 7-bit JTAG instruction register. See
page 7-81
for more details.
A reserved field is a field that may be used by an implementation. If the initial value
of a reserved field is supplied by software, this value must be zero. Software should
not modify reserved fields or depend on any values in reserved fields.
January, 2004
Intel XScale® Core Developer's Manual
®
core denoted by a CoreGen
Table 7-4, "ID Register" on
®
core denoted by a CoreGen
Table 7-4, "ID Register" on
Introduction
19
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