Mini-Data Cache Overview; Mini-Data Cache Organization - Intel XScale Core Developer's Manual

6.1.2

Mini-Data Cache Overview

The mini-data cache is 1/16
selected the available sizes are 2 K or 1 Kbytes. The 2 Kbyte version has 32 sets and the 1 Kbyte
version has 16 sets; both versions are 2-way set associative. Each way of a set contains 32 bytes
(one cache line) and one valid bit. There also exist 2 dirty bits for every line, one for the lower
16 bytes and the other one for the upper 16 bytes. When a store hits the cache the dirty bit
associated with it is set. The replacement policy is a round-robin algorithm.
Figure 6-2, "Mini-Data Cache Organization" on page 6-63
the data address is used to access the cache.
The mini-data cache is virtually addressed and virtually tagged and supports the same caching
policies as the data cache. However, lines can't be locked into the mini-data cache.
Figure 6-2.

Mini-Data Cache Organization

Example: 2K byte cache
Set Index
This example
shows Set 0
being selected by
the set index.
Word Select
Byte Select
Data Address (Virtual) - 2K byte cache
31
Data Address (Virtual) - 1K byte cache
31
Developer's Manual
th
the size of the data cache, so depending on the data cache size
Set 1
way 0
Set 0
way 1
way 0
way 1
Tag
Tag
Tag
January, 2004
Intel XScale® Core Developer's Manual
shows the cache organization and how
Set 31
way 0
way 1
32 bytes (cache line)
32 bytes (cache line)
Byte Alignment
Sign Extension
Data Word
(4 bytes to Destination Register)
Data Cache
32 bytes (cache line)
10 9 5 4 2
Set Index Word Byte
9 8 5 4 2
Set Index Word
1 0
1 0
63