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9.14.2
LDIC JTAG Command
The LDIC JTAG instruction selects the JTAG data register for loading code into the instruction
cache. The JTAG opcode for this instruction is '00111'. The LDIC instruction must be in the JTAG
instruction register in order to load code directly into the instruction cache through JTAG.
9.14.3
LDIC JTAG Data Register
The LDIC JTAG Data Register is selected when the LDIC JTAG instruction is in the JTAG IR. An
external host can load and invalidate lines in the instruction cache through this data register.
Figure 9-7.
LDIC JTAG Data Register Hardware
LDIC_SR1
LDIC_REG
LDIC_SR2
The data loaded into LDIC_SR1 during a Capture_DR is unpredictable.
All LDIC functions and data consists of 33 bit packets which are scanned into LDIC_SR1 during
the Shift_DR state.
Update_DR parallel loads LDIC_SR1 into LDIC_REG which is then synchronized with the
Elkhart clock and loaded into the LDIC_SR2. Once data is loaded into LDIC_SR2, the LDIC State
Machine turns on and serially shifts the contents if LDIC_SR2 to the instruction cache.
Note that there is a delay from the time of the Update_DR to the time the entire contents of
LDIC_SR2 have been shifted to the instruction cache. Removing the LDIC JTAG instruction from
the JTAG IR before the entire contents of LDIC_SR2 are sent to the instruction cache, will result in
unpredictable behavior. Therefore, following the Update_DR for the last LDIC packet, the LDIC
instruction must remain in the JTAG IR for a minimum of 15 TCKs. This ensures the last packet is
correctly sent to the instruction cache.
Developer's Manual
unpredictable
TDI
32
32
32
LDIC
State Machine
January, 2004
Intel XScale® Core Developer's Manual
Capture_DR
TDO
3
2
1
0
Update_DR
2
1
0
2
1
0
To Instruction Cache
Software Debug
TCK
Core CLK
155
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