Intel XScale Core Developer's Manual page 7

9.11.1.3 DCSR (DBG_SR[34:3])........................................................................ 140
9.11.2 DBGTX JTAG Register ........................................................................................141
9.11.2.1 DBG_SR[0] ..........................................................................................141
9.11.2.2 TX (DBG_SR[34:3]) ............................................................................. 141
9.11.3 DBGRX JTAG Register ....................................................................................... 142
9.11.3.1 RX Write Logic ..................................................................................... 143
9.11.3.2 DBG_SR[0] ..........................................................................................143
9.11.3.3 flush_rr ................................................................................................. 143
9.11.3.4 hs_download ........................................................................................143
9.11.3.5 RX (DBG_SR[34:3]) ............................................................................. 143
9.11.3.6 rx_valid................................................................................................. 144
9.12 Trace Buffer ...................................................................................................................... 145
9.12.1 Trace Buffer Registers ......................................................................................... 145
9.12.1.1 Checkpoint Registers ........................................................................... 146
9.12.1.2 Trace Buffer Register (TBREG) ........................................................... 147
9.13 Trace Buffer Entries .......................................................................................................... 148
9.13.1 Message Byte ......................................................................................................148
9.13.1.1 Exception Message Byte .....................................................................149
9.13.1.2 Non-exception Message Byte .............................................................. 150
9.13.1.3 Address Bytes ...................................................................................... 151
9.13.2 Trace Buffer Usage.............................................................................................. 152
9.14 Downloading Code in the Instruction Cache.....................................................................154
9.14.1 Mini Instruction Cache Overview ......................................................................... 154
9.14.2 LDIC JTAG Command ......................................................................................... 155
9.14.3 LDIC JTAG Data Register ...................................................................................155
9.14.4 LDIC Cache Functions......................................................................................... 156
9.14.5 Loading Instruction Cache During Reset ............................................................. 158
9.14.6 Dynamically Loading Instruction Cache After Reset............................................ 160
9.14.6.1 Dynamic Download Synchronization Code .......................................... 162
10 Performance Considerations ....................................................................................................... 163
10.1 Interrupt Latency ............................................................................................................... 163
10.2 Branch Prediction .............................................................................................................164
10.3 Addressing Modes ............................................................................................................ 164
10.4 Instruction Latencies ......................................................................................................... 165
10.4.1 Performance Terms ............................................................................................. 165
10.4.2 Branch Instruction Timings .................................................................................. 167
10.4.3 Data Processing Instruction Timings ................................................................... 167
10.4.4 Multiply Instruction Timings.................................................................................. 168
10.4.5 Saturated Arithmetic Instructions ......................................................................... 170
10.4.6 Status Register Access Instructions .................................................................... 170
10.4.7 Load/Store Instructions ........................................................................................171
10.4.8 Semaphore Instructions ....................................................................................... 171
10.4.9 Coprocessor Instructions ..................................................................................... 172
10.4.10 Miscellaneous Instruction Timing......................................................................... 172
10.4.11 Thumb Instructions .............................................................................................. 173
A Optimization Guide ...................................................................................................................... 175
A.1 Introduction ....................................................................................................................... 175
A.1.1 About This Guide ................................................................................................. 175
A.2 The Intel XScale
Developer's Manual
®
Core Pipeline....................................................................................... 176
January, 2004
Intel XScale® Core Developer's Manual
Contents
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