Register 14: Breakpoint Registers; Accessing The Debug Registers - Intel XScale Core Developer's Manual

7.2.14

Register 14: Breakpoint Registers

The Intel XScale
one data breakpoint address register (DBR0), one configurable data mask/address register (DBR1),
and one data breakpoint control register (DBCON).
Refer to Chapter 9, "Software Debug"
core.
Table 7-19.

Accessing the Debug Registers

Access Instruction Breakpoint
Control Register 0 (IBCR0)
Access Instruction Breakpoint
Control Register 1(IBCR1)
Access Data Breakpoint Address
Register (DBR0)
Access Data Mask/Address
Register (DBR1)
Access Data Breakpoint Control
Register (DBCON)
Developer's Manual
®
core contains two instruction breakpoint address registers (IBCR0 and IBCR1),
Function opcode_2
January, 2004
Intel XScale® Core Developer's Manual
for more information on these features of the Intel XScale
CRm
0b000 0b1000
0b000 0b1001
0b000 0b0000
0b000 0b0011
0b000 0b0100
Configuration
Instruction
MRC p15, 0, Rd, c14, c8, 0 ; read
MCR p15, 0, Rd, c14, c8, 0 ; write
MRC p15, 0, Rd, c14, c9, 0 ; read
MCR p15, 0, Rd, c14, c9, 0 ; write
MRC p15, 0, Rd, c14, c0, 0 ; read
MCR p15, 0, Rd, c14, c0, 0 ; write
MRC p15, 0, Rd, c14, c3, 0 ; read
MCR p15, 0, Rd, c14, c3, 0 ; write
MRC p15, 0, Rd, c14, c4, 0 ; read
MCR p15, 0, Rd, c14, c4, 0 ; write
®
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