Thumb Instructions - Intel XScale Core Developer's Manual

10.4.11

Thumb Instructions

In general, the timing of Thumb instructions are the same as their equivalent ARM instructions,
except for the cases listed below.
•
If the equivalent ARM instruction maps to one in
with Branch Misprediction" goes from 5 to 6 cycles. This is due to the branch latency penalty
(see Table
•
If the equivalent ARM instruction maps to one in
when the Branch is Taken" increases by 1 cycle. This is due to the branch latency penalty (see
Table
•
A Thumb BL instruction when H = 0 will have the same timing as an ARM data processing
instruction.
The mapping of Thumb instructions to ARM instructions can be found in the ARM Architecture
Reference Manual.
Developer's Manual
10-1).
10-1).
January, 2004
Intel XScale® Core Developer's Manual
Performance Considerations
Table 10-3, the "Minimum Issue Latency
Table 10-4, the "Minimum Issue Latency
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