Performance Monitor Control Register (Cp14, Register 0) - Intel XScale Core Developer's Manual

Intel XScale® Core Developer's Manual
Performance Monitoring
Table 8-4.

Performance Monitor Control Register (CP14, register 0)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: E and inten are 0, others unpredictable
Bits
31:28
27:20
19:12
11
10:8
7
6:4
3
2
1
0
104
evtCount1
Access
Read-unpredictable / Write-as-0
Read / Write
Read / Write
Read-unpredictable / Write-as-0
Read / Write
Read-unpredictable / Write-as-0
Read / Write
Read / Write
Read-unpredictable / Write
Read-unpredictable / Write
Read / Write
January, 2004
evtCount0 flag
Description
Reserved
Event Count1 - identifies the source of events that
PMN1 counts. See Table 8-12
values this field may contain.
Event Count0 - identifies the source of events that
PMN0 counts. See Table 8-12
values this field may contain.
Reserved
Overflow/Interrupt Flag - identifies which counter
overflowed
Bit 10 = clock counter overflow flag
Bit 9 = performance counter 1 overflow flag
Bit 8 = performance counter 0 overflow flag
Read Values:
0 = no overflow
1 = overflow has occurred
Write Values:
0 = no change
1 = clear this bit
Reserved
Interrupt Enable - used to enable/disable interrupt
reporting for each counter
Bit 6 = clock counter interrupt enable
0 = disable interrupt
1 = enable interrupt
Bit 5 = performance counter 1 interrupt enable
0 = disable interrupt
1 = enable interrupt
Bit 4 = performance counter 0 interrupt enable
0 = disable interrupt
1 = enable interrupt
Clock Counter Divider (D) -
0 = CCNT counts every processor clock cycle
1 = CCNT counts every 64
Clock Counter Reset (C) -
0 = no action
1 = reset the clock counter to '0x0'
Performance Counter Reset (P) -
0 = no action
1 = reset both performance counters to '0x0'
Enable (E) -
0 = all 3 counters are disabled
1 = all 3 counters are enabled
8 7 6 5 4 3 2 1 0
inten D C P E
for a description of the
for a description of the
th
processor clock cycle
Developer's Manual