Intel XScale Core Developer's Manual page 10

Intel XScale® Core Developer's Manual
Contents
Figures
1-1 Architecture Features ................................................................................................................. 16
3-1 Example of Locked Entries in TLB ............................................................................................. 45
4-1 Instruction Cache Organization .................................................................................................. 47
4-2 Locked Line Effect on Round Robin Replacement ..................................................................... 54
5-1 BTB Entry ................................................................................................................................... 57
5-2 Branch History ............................................................................................................................ 58
6-1 Data Cache Organization ........................................................................................................... 62
6-2 Mini-Data Cache Organization ................................................................................................... 63
6-3 Locked Line Effect on Round Robin Replacement ..................................................................... 74
9-1 SELDCSR................................................................................................................................. 139
9-2 DBGTX ..................................................................................................................................... 141
9-3 DBGRX ..................................................................................................................................... 142
9-4 Message Byte Formats............................................................................................................. 148
9-5 Indirect Branch Entry Address Byte Organization .................................................................... 151
9-6 High Level View of Trace Buffer ............................................................................................... 152
9-7 LDIC JTAG Data Register Hardware........................................................................................ 155
9-8 Format of LDIC Cache Functions ............................................................................................. 157
9-9 Code Download During a Cold Reset For Debug..................................................................... 158
9-10 Downloading Code in IC During Program Execution................................................................ 160
A-1 The Intel XScale
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Core RISC Superpipeline............................................................................ 177
January, 2004 Developer's Manual