Register 2: Translation Table Base Register; Register 3: Domain Access Control Register; Register 4: Reserved; Translation Table Base Register - Intel XScale Core Developer's Manual

7.2.3

Register 2: Translation Table Base Register

Table 7-8.

Translation Table Base Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: unpredictable
Bits
31:14
13:0
7.2.4

Register 3: Domain Access Control Register

Table 7-9.

Domain Access Control Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
D15 D14
reset value: unpredictable
Bits
31:0
7.2.5

Register 4: Reserved

Register 4 is reserved. Reading and writing this register yields unpredictable results.
Developer's Manual
Translation Table Base
Access
Read / Write
Read-unpredictable / Write-as-Zero
D13 D12 D11 D10
Access
Read / Write
January, 2004
Intel XScale® Core Developer's Manual
Translation Table Base - Physical address of the base of
the first-level table
Reserved
D9 D8 D7 D6 D5
Access permissions for all 16 domains - The meaning
of each field can be found in the ARM Architecture
Reference Manual .
Configuration
8 7 6 5 4 3 2
Description
8 7 6 5 4 3 2
D4 D3 D2 D1
Description
1 0
1 0
D0
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