Additions To Cp15 Functionality - Intel XScale Core Developer's Manual

2.3.3

Additions to CP15 Functionality

To accommodate the functionality in the Intel XScale
added or augmented. See
At times it is necessary to be able to guarantee exactly when a CP15 update takes effect. For
example, when enabling memory address translation (turning on the MMU), it is vital to know
when the MMU is actually guaranteed to be in operation. To address this need, a processor-specific
code sequence is defined for the core. The sequence -- called CPWAIT -- is shown in
on page 2-31.
Example 2-1. CPWAIT: Canonical method to wait for CP15 update
;; The following macro should be used when software needs to be
;; assured that a CP15 update has taken effect.
;; It may only be used while in a privileged mode, because it
;; accesses CP15.
MACRO CPWAIT
ENDM
When setting multiple CP15 registers, system software may opt to delay the assurance of their
update. This is accomplished by executing CPWAIT only after the sequence of MCR instructions.
Note: The CPWAIT sequence guarantees that CP15 side-effects are complete by the time the CPWAIT is
complete. It is possible, however, that the CP15 side-effect will take place before CPWAIT
completes or is issued. Programmers should take care that this does not affect the correctness of
their code.
Developer's Manual
Chapter 7, "Configuration"
MRC P15, 0, R0, C2, C0, 0
MOV R0, R0
SUB PC, PC, #4
; At this point, any previous CP15 writes are
; guaranteed to have taken effect.
January, 2004
Intel XScale® Core Developer's Manual
Programming Model
®
core, registers in CP15 and CP14 have been
for details.
; arbitrary read of CP15
; wait for it
; branch to next instruction
Example 2-1
31