Performance Monitoring; Overview - Intel XScale Core Developer's Manual

Performance Monitoring

This chapter describes the performance monitoring facility of the Intel XScale
that are monitored can provide performance information for compiler writers, system application
developers and software programmers.
There are two variants of the performance monitoring facility; the number, location and definition
of the registers are different between them. Software can determine which variant it is running on
by examining the CoreGen field of Coprocessor 15, ID Register (bits 15:13). (See
Register" on page 7-81
value of 0x2 is referred to as XSC2. The main difference between the two is that XSC1 has two
32-bit performance counters while XSC2 has four 32-bit performance counters.
8.1

Overview

The Intel XScale
unique events to be monitored simultaneously. In addition, the Intel XScale
32-bit clock counter that can be used in conjunction with the performance counters; its main
purpose is to count the number of core clock cycles which is useful in measuring total execution
time.
The Intel XScale
occurrence events, a counter is incremented each time a specified event takes place and when
measuring duration, a counter counts the number of processor clocks that occur while a specified
condition is true. If any of the counters overflow, an interrupt request will occur if it's enabled.
(What happens to the interrupt request is definable by the ASSP, which typically contains an
interrupt controller that handles priority, masking, steering to FIQ or IRQ, etc. Refer to the Intel
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XScale
details.) Each counter has its own interrupt request enable. The counters continue to monitor events
even after an overflow occurs, until disabled by software.
Each of these counters can be programmed to monitor any one of various events.
To further augment performance monitoring, the Intel XScale
measure the executing time of an application. This information combined with a duration event can
feedback a percentage of time the event occurred with respect to overall execution time.
All of the performance monitoring registers are accessible through Coprocessor 14 (CP14). Access
is allowed in privileged mode only. Note that these registers can't be accessed with LDC or STC
coprocessor instructions.
Developer's Manual
for more details.) A CoreGen value of 0x1 is referred to as XSC1 and a
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core hardware provides two or four 32-bit performance counters that allow
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core can monitor either occurrence events or duration events. When counting
core implementation option section of the ASSP architecture specification for more
January, 2004
Intel XScale® Core Developer's Manual
Performance Monitoring
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core implements a
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core clock counter can be used to
8
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core. The events
Table 7-4, "ID
101