Data Cache And Write Buffer; Data Cache And Buffer Behavior When X = 0; Data Cache And Buffer Behavior When X = 1 - Intel XScale Core Developer's Manual

3.2.2.4

Data Cache and Write Buffer

All of these descriptor bits affect the behavior of the Data Cache and the Write Buffer.
If the X bit for a descriptor is zero, the C and B bits operate as mandated by the ARM architecture.
This behavior is detailed in
If the X bit for a descriptor is one, the C and B bits' meaning is extended, as detailed in
Table 3-1.

Data Cache and Buffer Behavior when X = 0

C B Cacheable?
0 0
0 1
1 0
1 1
a. Normally, the processor will continue executing after a data access if no dependency on that access is encountered. With
this setting, the processor will stall execution until the data access completes. This guarantees to software that the data ac-
cess has taken effect by the time execution of the data access instruction completes. External data aborts from such access-
es will be imprecise (but see
Table 3-2.

Data Cache and Buffer Behavior when X = 1

C B Cacheable?
0 0
0 1
1 0
1 1
a. Normally, bufferable writes can coalesce with previously buffered data in the same address range
b. See Section 7.2.2
Developer's Manual
Table 3-1.
Bufferable?
N N
N Y
Y Y
Y Y
Section 2.3.4.4
Bufferable?
- -
N Y
(Mini Data
-
Cache)
Y Y
for a description of this register
January, 2004
Intel XScale® Core Developer's Manual
Line
Write Policy Allocation
Policy
- -
- -
Write Through Read Allocate
Write Back Read Allocate
for a method to shield code from this imprecision).
Line
Write Policy Allocation
Policy
- -
- -
- -
Read/Write
Write Back
Allocate
Memory Management
Table 3-2.
Notes
a
Stall until complete
Notes
Unpredictable -- do not use
Writes will not coalesce into
a
buffers
Cache policy is determined
by MD field of Auxiliary
b
Control register
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