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Table 2-2.
MIA{<cond>} acc0, Rm, Rs
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
cond
Operation: if ConditionPassed(<cond>) then
Exceptions: none
Qualifiers Condition Code
Notes:
The MIA instruction operates similarly to MLA except that the 40-bit accumulator is used. MIA
multiplies the signed value in register Rs (multiplier) by the signed value in register Rm
(multiplicand) and then adds the result to the 40-bit accumulator (acc0).
MIA does not support unsigned multiplication; all values in Rs and Rm will be interpreted as
signed data values. MIA is useful for operating on signed 16-bit data that was loaded into a general
purpose register by LDRSH.
The instruction is only executed if the condition specified in the instruction matches the condition
code status.
Table 2-3.
MIAPH{<cond>} acc0, Rm, Rs
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
cond
Operation: if ConditionPassed(<cond>) then
Exceptions: none
Qualifiers Condition Code
Notes:
The MIAPH instruction performs two16-bit signed multiplies on packed half word data and
accumulates these to a single 40-bit accumulator. The first signed multiplication is performed on
the lower 16 bits of the value in register Rs with the lower 16 bits of the value in register Rm. The
second signed multiplication is performed on the upper 16 bits of the value in register Rs with the
upper 16 bits of the value in register Rm. Both signed 32-bit products are sign extended and then
added to the value in the 40-bit accumulator (acc0).
The instruction is only executed if the condition specified in the instruction matches the condition
code status.
Developer's Manual
1 1 1 0 0 0 1 0 0 0 0 0
acc0 = (Rm[31:0] * Rs[31:0])[39:0] + acc0[39:0]
No condition code flags are updated
Early termination is supported. Instruction timings can be found
in
Section 10.4.4, "Multiply Instruction Timings" on page
Specifying R15 for register Rs or Rm has unpredictable results.
acc0 is defined to be 0b000 on the core.
1 1 1 0 0 0 1 0 1 0 0 0
acc0 = sign_extend(Rm[31:16] * Rs[31:16]) +
sign_extend(Rm[15:0] * Rs[15:0]) +
acc0[39:0]
S bit is always cleared; no condition code flags are updated
Instruction timings can be found
in
Section 10.4.4, "Multiply Instruction Timings" on page
Specifying R15 for register Rs or Rm has unpredictable results.
acc0 is defined to be 0b000 on the core
January, 2004
Intel XScale® Core Developer's Manual
Programming Model
8
7
6
Rs
0 0 0 0 0 0 0 1
8
7
6
Rs
0 0 0 0 0 0 0 1
5
4
3
2
1
0
Rm
10-168.
5
4
3
2
1
0
Rm
10-168.
25
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