Write Buffer/Fill Buffer Operation And Control - Intel XScale Core Developer's Manual

6.5

Write Buffer/Fill Buffer Operation and Control

See Section 1.3.2, "Terminology and Acronyms" on page 1-19
The write buffer is always enabled which means stores to external memory will be buffered. The
K bit in the Auxiliary Control Register (CP15, register 1) is a global enable/disable for allowing
coalescing in the write buffer. When this bit disables coalescing, no coalescing will occur
regardless the value of the page attributes. If this bit enables coalescing, the page attributes X, C,
and B are examined to see if coalescing is enabled for each region of memory.
All reads and writes to external memory occur in program order when coalescing is disabled in the
write buffer. If coalescing is enabled in the write buffer, writes may occur out of program order to
external memory. Program correctness is maintained in this case by comparing all store requests
with all the valid entries in the fill buffer.
The write buffer and fill buffer support a drain operation, such that before the next instruction
executes, all the core data requests to external memory have completed. Note that an ASSP may
also include operations external to the core in the drain operation. (Refer to the Intel XScale
implementation option section in the ASSP architecture specification for more details.) See
Table 7-12, "Cache Functions" on page 7-87
Writes to a region marked non-cacheable/non-bufferable (page attributes C, B, and X all 0) will
cause execution to stall until the write completes.
If software is running in a privileged mode, it can explicitly drain all buffered writes. For details on
this operation, see the description of Drain Write Buffer in
Functions" on page
Developer's Manual
for the exact command.
7-87.
January, 2004
Intel XScale® Core Developer's Manual
for a definition of coalescing.
Section 7.2.8, "Register 7: Cache
Data Cache
®
core
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