Loading Instruction Cache During Reset; Code Download During A Cold Reset For Debug - Intel XScale Core Developer's Manual

Intel XScale® Core Developer's Manual
Software Debug
9.14.5

Loading Instruction Cache During Reset

Code can be downloaded into the instruction cache through JTAG during a processor reset. This
feature is used during software debug to download the debug handler prior to starting a debug
session. Immediately out of reset, the downloaded handler can intercept the reset vector and turn
control of the system to the debugger. The debugger can then initialize the system as necessary and
begin the application program.
In general, any code downloaded into the instruction cache through JTAG, must be downloaded to
addresses that are not already valid in the instruction cache. Failure to meet this requirement will
result in unpredictable behavior by the processor. During a processor reset, the instruction cache is
typically invalidated, with the exception of the following cases:
•
When LDIC JTAG instruction is loaded in the JTAG IR, neither the mini instruction cache, nor
the main instruction cache are invalidated during reset.
•
When the Halt Mode bit is set in the DCSR only the mini instruction cache is prevented from
being invalidated during reset. The main instruction cache is still be invalidated.
The Figure 9-9
cold reset for debug.
Figure 9-9.

Code Download During a Cold Reset For Debug

Chip Reset Pin
Chip TRST
Core Reset Signal
(Internal)
SELDCSR.hold_reset
SELDCSR.halt_mode
SELDCSR.trap_reset
JTAG IR Value
and Debugger
JTAG Actions
indicates unknown value
1. The number of TCKs to wait is ASSP specific and can be found in the Implementation options section of
the ASSP architecture specification.
158
shows the actions necessary to download code into the instruction cache during a
de-assert Chip Reset AFTER SELDCSR.keep_rst is set
reset JTAG IR to IDCODE
Core Reset invalidates mini IC
Wait N
Chip Reset de-asserted
Read ID Reg value
SELDCSR
IDCODE
Set hold_reset bit
Set Halt Mode bit
Set Trap Reset bit
January, 2004
Halt Mode bit prevents
mini IC from being invalidated
hold_reset keeps core reset asserted
1
TCKs after Enter LDIC mode
Download code
LDIC
SELDCSR
Keep LDIC in IR
Reprogram SELDCSR
for 20 TCKs after
Set hold_reset bit
last update_dr
Set Halt Mode bit
Set Trap Reset bit
Reset Vector Trap
generated out of reset
Clear hold_reset bit
Set Halt Mode bit
Set Trap Reset bit
SELDCSR DBGTX
Poll DBGTX to
detect debug break
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