Reset; Update Policy; Branch History - Intel XScale Core Developer's Manual

Intel XScale® Core Developer's Manual
Branch Target Buffer
The history bits represent four possible prediction states for a branch entry in the BTB.
"Branch History" on page 5-58
state for branches stored in the BTB is Weakly-Taken (WT). Every time a branch that exists in the
BTB is executed, the history bits are updated to reflect the latest outcome of the branch, either
taken or not-taken.
Chapter 10, "Performance Considerations"
by the BTB and the performance penalty for mispredicting a branch.
The BTB does not have to be managed explicitly by software; it is disabled by default after reset
and is invalidated when the instruction cache is invalidated.
Figure 5-2.

Branch History

Not
Taken
5.1.1

Reset

After Processor Reset, the BTB is disabled and all entries are invalidated.
5.1.2

Update Policy

A new entry is stored into the BTB when the following conditions are met:
•
the branch instruction has executed,
•
the branch was taken
•
the branch is not currently in the BTB
The entry is then marked valid and the history bits are set to WT. If another valid branch exists at
the same entry in the BTB, it will be evicted by the new branch.
Once a branch is stored in the BTB, the history bits are updated upon every execution of the branch
as shown in
58
shows these states along with the possible transitions. The initial
Taken
WN
SN
Not Taken
Not Taken
SN: Strongly Not Taken
WN: Weakly Not Taken
Figure 5-2.
January, 2004
describes which instructions are dynamically predicted
Taken
WT
ST: Strongly Taken
WT: Weakly Taken
Figure 5-2,
Taken
ST
Taken
Not Taken
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