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Intel XScale® Core Developer's Manual
Performance Monitoring
8.6.2
XSC2 Example (4 counter variant)
In this example, the events selected with the Instruction Cache Efficiency mode are monitored and
CCNT is used to measure total execution time. Sampling time ends when PMN0 overflows which
will generate an IRQ interrupt.
Example 8-4. Configuring the Performance Monitor
; Configure the performance monitor with the following values:
;
EVTSEL.evtCount0 = 7, EVTSEL.evtCount1 = 0 instruction cache efficiency
;
INTEN.inten = 0x7 set all counters to trigger an interrupt on overflow
;
PMNC.C = 1
;
PMNC.P = 1
;
PMNC.E = 1
MOV
R0,#0x700
MCR
P14,0,R0,C8,c1,0
MOV
R0,#0x7
MCR
P14,0,R0,C4,c1,0
MCR
P14,0,R0,C0,c1,0
; Counting begins
Counter overflow can be dealt with in the IRQ interrupt service routine as shown below:
Example 8-5. Interrupt Handling
IRQ_INTERRUPT_SERVICE_ROUTINE:
; Assume that performance counting interrupts are the only IRQ in the system
MRC
P14,0,R1,C0,c1,0
BIC
R2,R1,#1
MCR
P14,0,R2,C0,c1,0
MRC
P14,0,R3,C1,c1,0
MRC
P14,0,R4,C0,c2,0
MRC
P14,0,R5,C1,c2,0
<process the results>
SUBS PC,R14,#4
As an example, assume the following values in CCNT, PMN0, PMN1 and PMNC:
Example 8-6. Computing the Results
; Assume CCNT overflowed
CCNT = 0x0000,0020 ;Overflowed and continued counting
Number of instructions executed = PMN0 = 0x6AAA,AAAA
Number of instruction cache miss requests = PMN1 = 0x0555,5555
Instruction Cache miss-rate = 100 * PMN1/PMN0 = 5%
CPI = (CCNT + 2^32)/Number of instructions executed = 2.4 cycles/instruction
In the contrived example above, the instruction cache had a miss-rate of 5% and CPI was 2.4.
120
reset CCNT register
reset PMN0 and PMN1 registers
enable counting
; setup EVTSEL
; setup INTEN
; setup PMNC, reset counters & enable
; read the PMNC register
; clear the enable bit, preserve other bits in PMNC
; disable counting
; read CCNT register
; read PMN0 register
; read PMN1 register
; return from interrupt
January, 2004
Developer's Manual
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