Debug Control And Status Register (Dcsr) - Intel XScale Core Developer's Manual

9.4

Debug Control and Status Register (DCSR)

The DCSR register is the main control register for the debug unit.
the register. The DCSR register can be accessed in privileged modes by software running on the
core or by a debugger through the JTAG interface. Refer to
Register"
Table 9-1. Debug Control and Status Register (DCSR) (Sheet 1 of 2)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
GE H B
Bits Access
SW Read / Write
31
JTAG Read-Only
SW Read Only
30
JTAG Read / Write
SW Read-Only
29
JTAG Read-Only
28:24 Read-undefined / Write-As-Zero
SW Read Only
23
JTAG Read / Write
SW Read Only
22
JTAG Read / Write
21 Read-undefined / Write-As-Zero
SW Read Only
20
JTAG Read / Write
SW Read Only
19
JTAG Read / Write
SW Read Only
18
JTAG Read / Write
SW Read Only
17
JTAG Read / Write
SW Read Only
16
JTAG Read / Write
Developer's Manual
for details about accessing DCSR through JTAG.
TF TI TD TA TS TU TR
Global Enable (GE)
0: disables all debug functionality
1: enables all debug functionality
Halt Mode (H)
0: Monitor Mode
1: Halt Mode
SOC Break (B)
Value of SOC break core input
Reserved
Trap FIQ (TF)
Trap IRQ (TI)
Reserved
Trap Data Abort (TD)
Trap Prefetch Abort (TA)
Trap Software Interrupt (TS)
Trap Undefined Instruction (TU)
Trap Reset (TR)
January, 2004
Intel XScale® Core Developer's Manual
Table 9-1
Section 9.11.1, "SELDCSR JTAG
9 8
Description
Software Debug
shows the format of
7 6 5 4 3 2 1 0
SA MOE M E
Reset Value TRST Value
0 unchanged
unchanged 0
undefined undefined
undefined undefined
unchanged 0
unchanged 0
undefined undefined
unchanged 0
unchanged 0
unchanged 0
unchanged 0
unchanged 0
123