Test Features; Overview; B.1 Overview - Intel XScale Core Developer's Manual

Test Features

This chapter gives a brief overview of the Intel XScale
core provides a baseline set of features from with the ASSP builds upon. A full description of these
features can be found in the ASSP architecture specification.
B.1

Overview

The Intel XScale
Boundary Scan Architecture (IEEE Std. 1149.1). These features include a TAP controller, a 5 or 7
bit instruction register, and test data registers to support software debug. The size of the instruction
register depends on which variant of the Intel XScale
examining the CoreGen field of Coprocessor 15, ID Register (bits 15:13). (See
Register" on page 7-81
register size is 5 bits and a CoreGen value of 0x2 means the JTAG instruction register size is 7 bits.
The Intel XScale
ID register, and other data test register specific to ASSP implementation.
To avoid confusion and duplication, the description of these features are in the ASSP architecture
specification.
Developer's Manual
®
core provides test features compatible with IEEE Standard Test Access Port and
for more details.) A CoreGen value of 0x1 means the JTAG instruction
®
core also provides support for an ASSP defined boundary-scan register, device
January, 2004
Intel XScale® Core Developer's Manual
®
core JTAG features. The Intel XScale
®
core is being used. This can be found out by
Test Features
B
®
Table 7-4, "ID
219