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9.11.2
DBGTX JTAG Register
The 'DBGTX' JTAG instruction selects the DBGTX JTAG data register. The JTAG opcode for this
instruction is '0b0010000'. The debug handler uses the DBGTX data register to send data to the
debugger. A protocol can be setup between the debugger and debug handler to allow the debug handler
to signal an entry into debug mode, and once in debug mode to transmit data requested by the debugger.
Figure 9-2.
DBGTX
Capture_DR
TDI
Update_DR
A Capture_DR loads the TX register value into DBG_SR[34:3] and TXRXCTRL.TR into
DBG_SR[0]. The other bits in DBG_SR are loaded as shown in
The captured TX value is scanned out during the Shift_DR state. Transitioning from Shift_DR
immediately to Capture_DR after capturing a '1' in DBG_SR[0] automatically clears TXRXCTRL.TR.
Data scanned in is ignored on an Update_DR.
9.11.2.1
DBG_SR[0]
DBG_SR[0] is used for part of the synchronization that occurs between the debugger and debug
handler for accessing TX. The debugger polls DBG_SR[0] to determine when the TX register
contains valid data from the debug handler.
A '1' captured in DBG_SR[0] indicates the captured TX data is valid. After capturing valid data, the
debugger must place the JTAG state machine in the Shift_DR state to guarantee that a debugger read
clears TXRXCTRL.TR. A '0' indicates there is no new data from the debug handler in the TX register.
9.11.2.2
TX (DBG_SR[34:3])
DBG_SR[34:3] is updated with the contents of the TX register following an Update_DR.
Note: If DBG_SR[0] is '0' following an Update_DR, the contents of DBG_SR[34:3] are unpredictable.
Developer's Manual
software write
TX
31
0
0
35
34
3
2
Ignored
January, 2004
Intel XScale® Core Developer's Manual
set by SW write to TX
0
Core CLK
TCLK
1
cleared by Debugger read
TDO
DBG_SR
1
0
Figure
Software Debug
software read-only
TXRXCTRL
28
9-1.
141
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