Table of Contents
Advertisement
8.3.2
Performance Count Registers (PMN0 - PMN3)
There are four 32-bit event counters; their format is shown in
reset to '0' by setting bit 1 in the PMNC register or can be set to a predetermined value by directly
writing to them. When an event counter reaches its maximum value 0xFFFF,FFFF, the next event it
needs to count will cause it to roll over to zero and set its corresponding overflow flag
(bit 1,2,3 or 4) in FLAG. An interrupt request will be generated if its corresponding interrupt enable
(bit 1,2,3 or 4) is set in INTEN.
Table 8-7.
Performance Monitor Count Register (PMN0 - PMN3)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: unpredictable
Bits
31:0
Developer's Manual
Access
Read / Write
January, 2004
Intel XScale® Core Developer's Manual
Table
Event Counter
Description
32-bit event counter - Reset to '0' by PMNC register.
When an event counter reaches its maximum value
0xFFFF,FFFF, the next event it needs to count will cause
it to roll over to zero and generate an interrupt request if
enabled.
Performance Monitoring
8-7. The event counters are
8
7
6
5
4
3
2
1
0
107
Advertisement
Table of Contents
