Load/Store Instructions; Semaphore Instructions; Load And Store Instruction Timings; Load And Store Multiple Instruction Timings - Intel XScale Core Developer's Manual

10.4.7

Load/Store Instructions

Table 10-11. Load and Store Instruction Timings
Mnemonic
LDR
LDRB
LDRBT
LDRD
LDRH
LDRSB
LDRSH
LDRT
PLD
STR
STRB
STRBT
STRD
STRH
STRT
Table 10-12. Load and Store Multiple Instruction Timings
Mnemonic
a
LDM
STM
a. See Table 10-4
b. numreg is the number of registers in the register list
10.4.8

Semaphore Instructions

Table 10-13. Semaphore Instruction Timings
Mnemonic
SWP
SWPB
Developer's Manual
Minimum Issue Latency
1
1
1
1 (+1 if Rd is R12)
1
1
1
1
1
1
1
1
2
1
1
Minimum Issue Latency
b
2 + numreg
2 + numreg
for LDM timings when R15 is in the register list
Minimum Issue Latency
5
5
January, 2004
Intel XScale® Core Developer's Manual
Performance Considerations
Minimum Result Latency
3 for load data; 1 for writeback of base
3 for load data; 1 for writeback of base
3 for load data; 1 for writeback of base
3 for Rd; 4 for Rd+1;
1 (+1 if Rd is R12) for writeback of base
3 for load data; 1 for writeback of base
3 for load data; 1 for writeback of base
3 for load data; 1 for writeback of base
3 for load data; 1 for writeback of base
N/A
1 for writeback of base
1 for writeback of base
1 for writeback of base
2 for writeback of base
1 for writeback of base
1 for writeback of base
Minimum Result Latency
5-18 for load data (4 + numreg for last register
in list; 3 + numreg for 2nd to last register in list;
2 + numreg for all other registers in list);
2+ numreg for writeback of base
2 + numreg for writeback of base
Minimum Result Latency
5
5
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